公开(公告)号：US11665405B2

公开(公告)日：2023-05-30

申请号：US17588936

申请日：2022-01-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Noritaka Iguchi ,  Tadamasa Toma ,  Hisaya Katou

IPC: H04N7/20 ,  H04N21/643 ,  H04L69/04 ,  H04L69/22 ,  H04L69/28 ,  H04N21/242 ,  H04N21/43 ,  H04N21/61 ,  H04N21/845 ,  H04N21/8547 ,  H04L61/5007 ,  H04L69/32 ,  H04J3/06

CPC classification number: H04N21/64322 ,  H04L61/5007 ,  H04L69/04 ,  H04L69/22 ,  H04L69/28 ,  H04L69/32 ,  H04N21/242 ,  H04N21/4302 ,  H04N21/6125 ,  H04N21/6143 ,  H04N21/6175 ,  H04N21/6193 ,  H04N21/845 ,  H04N21/8547 ,  H04J3/0667

Abstract: A transmission method includes: generating one or more transfer frames that each store one or more streams used for content transfer; and transmitting the one or more generated frames through broadcast, each of the one or more streams storing one or more second transfer units, each of the one or more second transfer units storing one or more first transfer units, and each of the one or more first transfer units storing one or more Internet Protocol (IP) packets. In at least one stream among the one or more streams, each of the first transfer units positioned at a head contains reference clock information indicating time used for reproduction of the content.

公开(公告)号：US11616956B2

公开(公告)日：2023-03-28

申请号：US17308397

申请日：2021-05-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Jing Ya Li ,  Han Boon Teo ,  Ru Ling Liao ,  Che Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe

IPC: H04N19/13 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, determines whether a first block is available and whether a second block is available, the first block and the second block being defined relative to a current block to be processed; selects a context model based on whether the first block is available, whether the second block is available, which of inter prediction and intra prediction is to be applied to the first block, and which of inter prediction and intra prediction is to be applied to the second block; and encodes, using the context model selected, a parameter indicating which of intra prediction and inter prediction is to be applied to the current block.

公开(公告)号：US11611758B2

公开(公告)日：2023-03-21

申请号：US16795408

申请日：2020-02-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro NIshi ,  Tadamasa Toma ,  Yusuke Kato

IPC: G06V30/00 ,  H04N19/159 ,  H04N19/126 ,  H04N19/156 ,  H04N19/18 ,  H04N19/52 ,  H04N19/61

Abstract: An image encoder is provided including circuitry and a memory coupled to the circuitry. The circuitry, in operation, responds to a size of a block satisfying a size condition by generating a prediction image using a prediction mode selected from a plurality of prediction modes. The plurality of prediction modes include a first prediction mode in which a prediction process uses a motion vector and a reference block in a same picture as the block. The circuitry encodes the block using the prediction image.

公开(公告)号：US11601669B2

公开(公告)日：2023-03-07

申请号：US17534898

申请日：2021-11-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/513 ,  H04N19/132 ,  H04N19/176 ,  H04N19/563

Abstract: The present disclosure provides systems and methods for video coding. The systems include, for example, an image encoder comprising: circuitry; and a memory coupled to the circuitry, wherein the circuitry, in operation, performs the following: predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture; padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block; calculating at least a gradient using the second block of prediction samples; and encoding the current block using at least the calculated gradient.

公开(公告)号：US11575931B2

公开(公告)日：2023-02-07

申请号：US17476947

申请日：2021-09-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Takashi Hashimoto

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/182 ,  H04N19/513

Abstract: Provided is an encoder that achieves further improvement. The encoder includes processing circuitry and memory. Using the memory, the processing circuitry: obtains two prediction images from two reference pictures; derives a luminance gradient value of each pixel position in each of the two prediction images; derives a luminance local motion estimation value of each pixel position in a current block; generates a luminance final prediction image using a luminance value and the luminance gradient value in each of the two prediction images, and the luminance local motion estimation value of the current block; and generates a chrominance final prediction image using at least one of the luminance gradient value of each of the two prediction images or the luminance local motion estimation value of the current block, and chrominance of each of the two prediction images.

公开(公告)号：US11575896B2

公开(公告)日：2023-02-07

申请号：US17120995

申请日：2020-12-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hideo Saitou ,  Masato Ohkawa ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/18 ,  H04N19/124 ,  H04N19/136 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: generates (i) a first quantization matrix for transform coefficients included in a current block to be processed and (ii) a second quantization matrix for transform coefficients included in a low frequency domain among the transform coefficients included in the current block; and quantizes the transform coefficients included in the current block using at least one of the first quantization matrix or the second quantization matrix, in accordance with a size of the current block.

公开(公告)号：US11575892B2

公开(公告)日：2023-02-07

申请号：US17532766

申请日：2021-11-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Sughosh Pavan Shashidhar ,  Hai Wei Sun ,  Chong Soon Lim ,  Ru Ling Liao ,  Han Boon Teo ,  Jing Ya Li ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh ,  Tadamasa Toma

IPC: H04N11/02 ,  H04N19/119 ,  H04N19/176 ,  H04N19/184 ,  H04N19/60

Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; and encodes the plurality of sub blocks.

公开(公告)号：US11570432B2

公开(公告)日：2023-01-31

申请号：US17141440

申请日：2021-01-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/117 ,  H04N19/136 ,  H04N19/159 ,  H04N19/176 ,  H04N19/182 ,  H04N19/61 ,  H04N19/82

Abstract: A decoder includes a memory and processing circuitry. The processing circuitry, in operation, changes values of pixels in a first block and a second block to filter a boundary therebetween, using clipping such that change amounts of the respective values are within respective clip widths. The clip widths for the pixels in the first block and the second block are selected based on block sizes of the first block and the second block. The pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary. The clip widths include a first clip width and a second clip width corresponding to the first pixel and the second pixel, respectively, and the first clip width is different from the second width.

公开(公告)号：US11546591B2

公开(公告)日：2023-01-03

申请号：US17667871

申请日：2022-02-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Che Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/117 ,  H04N19/105 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).

公开(公告)号：US11533511B2

公开(公告)日：2022-12-20

申请号：US17591259

申请日：2022-02-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato Ohkawa ,  Hideo Saitou ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/112 ,  H04N19/12 ,  H04N19/16 ,  H04N19/186 ,  H04N19/60 ,  H04N19/119 ,  H04N19/17 ,  H04N19/184 ,  H04N19/30

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. In operation, the circuitry: performs a mapping process of Luma Mapping with Chroma Scaling (LMCS) for transforming a first pixel value space applied to a luma display image signal into a second pixel value space applied to a luma encoding process signal, using line segments forming a transform curve, each of which corresponds to a different one of sections obtained by partitioning the first pixel value space; and encodes an image, and in the performing of the LMCS, the circuitry determines the transform curve so that among boundary values in the second pixel value space, a first value obtained by dividing a boundary value by a base width defined according to a bit depth of the image is not equal to a second value obtained by dividing another boundary value by the base width.