公开(公告)号：US07103058B2

公开(公告)日：2006-09-05

申请号：US10036602

申请日：2001-12-21

Applicant: Abbas Rashid ,  Nazar Zaidi ,  Mark Bryers

Inventor： Abbas Rashid ,  Nazar Zaidi ,  Mark Bryers

IPC: H04L12/56 ,  H04L12/28 ,  H04L12/24

CPC classification number: H04L49/102 ,  H04L12/42 ,  H04L41/0896 ,  H04L49/101 ,  H04L49/201 ,  H04L49/205 ,  H04L49/25 ,  H04L49/3018

Abstract: A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to accept data packets targeted to destinations supported by the sink port. The cross-bar switch includes a multi-sink port for supporting explicit multicast addressing. The multi-sink port is coupled to each data ring and each sink port. The multi-sink port snoops multicast packets on the cross-bar switch's rings and transfers each packet to a set of sink ports that support the packet's targeted destinations.

Abstract translation: 交叉开关包括用于接收数据分组的一组输入端口和用于将接收到的分组发送到识别的目标的一组接收端口。 一组数据环将输入端口耦合到接收端口。 每个宿端口都使用一组数据环来接收由宿端口支持的目的地的数据包。 交叉开关包括用于支持显式多播寻址的多宿端口。 多宿端口耦合到每个数据环和每个宿端口。 多汇端口监听交叉开关环上的组播数据包，并将每个数据包传输到支持数据包目标目的地的一组接收端口。

公开(公告)号：US20050044324A1

公开(公告)日：2005-02-24

申请号：US10930939

申请日：2004-08-31

Applicant: Abbas Rashid ,  David Hass

Inventor： Abbas Rashid ,  David Hass

IPC: G06F12/08 ,  H04L12/56 ,  G06F12/14 ,  G06F13/00

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/15

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。