公开(公告)号：US11909638B2

公开(公告)日：2024-02-20

申请号：US17237026

申请日：2021-04-21

Applicant: Syntropy Network Limited

Inventor： Jonas Simanavicius ,  William B. Norton ,  Domas Povilauskas ,  Jim X. Wen

IPC: G06F15/16 ,  H04L45/00 ,  H04L45/021 ,  H04L49/102 ,  H04L43/0852

CPC classification number: H04L45/70 ,  H04L43/0858 ,  H04L45/021 ,  H04L49/102

Abstract: A method is disclosed for autonomously routing data using relay nodes pre-selected from a group of distributed computer nodes based on measured one-way latencies. One-way latencies between a plurality of nodes in a pulse group are automatically measured. A sending bucket of nodes are automatically selected from the pulse group based on the one-way latencies. A receiving bucket of nodes are automatically selected from the pulse group based on the one-way latencies. In response to a command to transfer data from the first node to the second node, a relay node that is both in the first sending bucket and in the first receiving bucket is automatically selected, wherein data is automatically routed from the first node to the second node via the relay node.

公开(公告)号：US11671382B2

公开(公告)日：2023-06-06

申请号：US15185864

申请日：2016-06-17

Applicant: Intel Corporation

Inventor： John J. Browne ,  Seán Harte ,  Tomasz Kantecki ,  Pierre Laurent ,  Chris MacNamara

IPC: H04N21/443 ,  H04L49/9057 ,  H04N21/426 ,  H04L49/103 ,  H04L1/00 ,  H04L49/102 ,  H04L49/00 ,  H04L49/9005 ,  H04N21/232

CPC classification number: H04L49/9057 ,  H04L1/0016 ,  H04L49/102 ,  H04L49/103 ,  H04L49/3063 ,  H04N21/42692 ,  H04N21/4435 ,  H04L1/002 ,  H04L49/9005 ,  H04N21/2326

Abstract: Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.

公开(公告)号：US10382326B1

公开(公告)日：2019-08-13

申请号：US15986476

申请日：2018-05-22

Applicant: Juniper Networks, Inc.

Inventor： Ravi Singh ,  Kireeti Kompella

IPC: H04L12/723 ,  H04L12/933 ,  H04L12/755

CPC classification number: H04L45/50 ,  H04L12/185 ,  H04L12/422 ,  H04L45/021 ,  H04L45/16 ,  H04L47/724 ,  H04L49/102

Abstract: Techniques are described for detecting egress network devices of a point-to-multipoint (P2MP) label switched path (LSP). For example, a network device may include one or more processors configured to identify a P2MP LSP for receiving multicast traffic from a multicast source for a specific multicast group for which the network device has an interested receiver, wherein the network device is to be an egress network device of the P2MP LSP; and send, to an ingress network device of the P2MP LSP, a P2MP egress identification message to add the network device as an egress network device of the P2MP LSP, wherein the one or more processors are further configured to output the P2MP egress identification message into a multipoint-to-point (MP2P) ring LSP for which the ingress network device of the P2MP LSP is a sole egress network device of the MP2P ring LSP.

公开(公告)号：US20180227112A1

公开(公告)日：2018-08-09

申请号：US15886912

申请日：2018-02-02

Applicant: Huawei Technologies Co., Ltd.

Inventor： Qiaoshi Zheng ,  Zhirui Chen ,  Jing Xia

IPC: H04L5/22 ,  H04Q11/08 ,  H04L12/933 ,  G06F9/30

CPC classification number: H04L5/22 ,  G06F9/30134 ,  H04L49/102 ,  H04L2012/5612 ,  H04L2012/5675 ,  H04Q11/08

Abstract: A bufferless ring network including at least two nodes and at least two timeslots, the at least two timeslots include a dedicated timeslot, and a first node in the bufferless ring network has use permission for the dedicated timeslot. The first node is configured to, in a state of having the use permission for the dedicated timeslot, detect whether all dedicated timeslots that pass through the first node are available, set a permission switch signal, and cancel the use permission for the dedicated timeslot according to the permission switch signal after detecting that all the dedicated timeslots that pass through the first node are available. A remaining node in the bufferless ring network is configured to obtain the use permission for the dedicated timeslot according to the permission switch signal. The remaining node is a node that needs to use the dedicated timeslot.

公开(公告)号：US20180212899A1

公开(公告)日：2018-07-26

申请号：US15884911

申请日：2018-01-31

Applicant: Konda Technologies Inc.

Inventor： Venkat Konda

IPC: H04L12/933

CPC classification number: H04L49/1515 ,  H04L49/102

Abstract: Significantly optimized multi-stage networks with scheduling methods for faster scheduling of connections, useful in wide target applications, with VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each block employ several slices of rings of stages of switches with inlet and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand side only, or from both left-hand side and right-hand side; and employ multi-drop links where outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are connected to either inlet links of switches in the another stage of a ring in the same or another sub-integrated circuit block

公开(公告)号：US20180198734A1

公开(公告)日：2018-07-12

申请号：US15403723

申请日：2017-01-11

Applicant: NetSpeed Systems, Inc.

Inventor： Pier Giorgio RAPONI ,  Nishant RAO ,  Sailesh KUMAR

IPC: H04L12/933 ,  H04L12/761 ,  H04L12/773 ,  H04L12/751

CPC classification number: H04L49/109 ,  H04L45/02 ,  H04L45/16 ,  H04L45/60 ,  H04L49/102

Abstract: The present disclosure is directed to extracting features from a NoC for machine learning construction. Example implementations include a method for generating a Network on Chip (NoC), wherein the method can extract at least one feature from a NoC specification to derive at least one of: grid features, traffic features and topological features associated with the NoC. The method can perform a process on the at least one of the grid features, the traffic features and the topological features associated with the NoC to determine at least one of an evaluation of at least one mapping strategy selected from a plurality of mapping strategies of the NoC based on a quality metric, and the selection of the at least one mapping strategy is based on the quality metric. The method can further perform generate the NoC based on the process.

公开(公告)号：US20180176150A1

公开(公告)日：2018-06-21

申请号：US15887211

申请日：2018-02-02

Applicant: GVBB HOLDINGS S.A.R.L.

Inventor： Charles S. MEYER ,  Ken BUTTLE

IPC: H04L12/933 ,  H04N5/262 ,  H04L12/931 ,  H04L12/721 ,  H04L12/947

CPC classification number: H04L49/101 ,  H04L45/66 ,  H04L49/102 ,  H04L49/206 ,  H04L49/25 ,  H04L49/35 ,  H04N5/262

Abstract: A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device.

公开(公告)号：US09942174B2

公开(公告)日：2018-04-10

申请号：US14641197

申请日：2015-03-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Yoshida ,  Tomoki Ishii ,  Satoru Tokutsu ,  Takao Yamaguchi ,  Yuuki Soga

IPC: H04L12/861 ,  H04L12/801 ,  H04L12/933 ,  G06F13/16 ,  G06F21/85

CPC classification number: H04L49/9057 ,  G06F13/1626 ,  G06F13/1673 ,  G06F21/85 ,  G06F2221/2141 ,  H04L47/34 ,  H04L49/102

Abstract: A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.

公开(公告)号：US20180083827A1

公开(公告)日：2018-03-22

申请号：US15562164

申请日：2016-03-04

Applicant: HONDA MOTOR CO., LTD.

Inventor： Ryusuke Ishizaki

IPC: H04L12/24 ,  H04L29/06 ,  H04L12/933

CPC classification number: H04L41/0677 ,  H04L12/427 ,  H04L12/433 ,  H04L49/102 ,  H04L69/22

Abstract: A communication system wherein, in each node, data transmission blocks transmit transmission data, and data relay blocks relay the transmission data from another node in a prior stage as relay data. Output switching units switch between outputting the transmission data and outputting the relay data as output data.

公开(公告)号：US20170085475A1

公开(公告)日：2017-03-23

申请号：US15080429

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Scott Wang-Yip Cheng ,  Raheel Khan ,  Vijay Bantval ,  Jun Ho Bahn

IPC: H04L12/741 ,  H04L12/413 ,  H04L1/00 ,  H04L12/46 ,  H04L12/733

CPC classification number: H04L45/74 ,  H04L1/0018 ,  H04L12/4135 ,  H04L12/42 ,  H04L12/4637 ,  H04L45/22 ,  H04L45/306 ,  H04L49/102 ,  H04L49/109

Abstract: Various aspects of this disclosure describe a bi-directional, dual interconnect bus configured in a ring to route data to processors implementing modem functions. A plurality of nodes may be coupled to form a ring bus comprising at least two interconnect rings. A plurality of processors may be assigned to the plurality of nodes. A first processor among the plurality of processors may be configured to process a first data type, and a second processor among the plurality of processors may be configured to process a second data type. Data on the ring bus may be separated into the first data type and the second data type, and separated data of the first data type may be routed on one interconnect ring to the first processor and separated data of the second data type may be routed on another interconnect ring to the second processor.