公开(公告)号：US20110082949A1

公开(公告)日：2011-04-07

申请号：US12996996

申请日：2008-06-10

Applicant: David L. Matthews ,  Hubert E. Brinkmann ,  James Xuan Dinh ,  Dwight D. Riley ,  Paul V. Brownell

Inventor： David L. Matthews ,  Hubert E. Brinkmann ,  James Xuan Dinh ,  Dwight D. Riley ,  Paul V. Brownell

IPC: G06F3/00 ,  G06F9/00

CPC classification number: H04L12/28 ,  G06F13/4027

Abstract: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

Abstract translation: 在一个实施例中，计算机系统包括至少一个主机节点，耦合到主机节点的至少一个输入/输出节点，经由交换机耦合到输入/输出节点的至少一个多功能设备，以及中间管理器 处理器包括用于阻止主机节点中用于交换机层级之后的多功能设备的枚举过程的逻辑，为与主机节点分离的管理器处理器中的多功能设备启动枚举过程，存储用于交换机的路由表 耦合到管理器处理器的存储器模块中的层次结构，并且在管理器处理器中将端点设备资源分配给主机节点。

公开(公告)号：US07340545B2

公开(公告)日：2008-03-04

申请号：US11203733

申请日：2005-08-15

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F13/362

CPC classification number: G06F13/423

Abstract: There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to establish an isochronous channel between a first device and a second device, establishing the isochronous channel between the first device and the second device, and generating an isochronous transaction across the isochronous channel between the first device and the second device, wherein the isochronous transaction is a message type transaction.

Abstract translation: 提供了一种用于计算机系统的互连总线的分布式对等通信系统。 更具体地，提供了一种方法，包括发送在第一设备和第二设备之间建立同步信道的请求，在第一设备和第二设备之间建立同步信道，以及在等时信道之间生成同步事务 第一设备和第二设备，其中等时事务是消息类型事务。

公开(公告)号：US06801970B2

公开(公告)日：2004-10-05

申请号：US09968056

申请日：2001-09-30

Applicant: Dwight D. Riley ,  Chris Pettey

Inventor： Dwight D. Riley ,  Chris Pettey

IPC: G06F1340

CPC classification number: G06F13/423 ,  G06F2213/0024

Abstract: Support for indicating and controlling transaction priority on a PCI-X bus. Embodiments of the invention provide indicia that can be set to communicate to PCI-X-to-PCI-X bridges and Completer that a transaction should be handled specially and scheduled ahead of any other transaction not having their corresponding indicia set. A special handling instruction allows the priority transaction to be scheduled first or early. The indicia are implemented by setting a bit(s) in an unused portion of a PCI-X attribute field, or multiplexed with a used portion, to schedule the associated transaction as the priority transaction over other transactions that do not have their corresponding bit set. The present invention can be used for interrupt messaging, audio streams, video streams, isochronous transactions, or for high performance, low bandwidth control structures used for communication in a multiprocessor architecture across PCI-X.

Abstract translation: 支持指示和控制PCI-X总线上的事务优先级。 本发明的实施例提供了可以设置为与PCI-X到PCI-X网桥通信的标记，并且完成事务应当在没有其对应标记集的任何其他事务之前特别处理和调度。 特殊处理指令允许首先或早期安排优先级事务。 通过在PCI-X属性字段的未使用部分中设置一个或多个与所使用的部分进行复用的位来实施该标记，以将相关联的事务调度为不具有其对应位集合的其他事务的优先级事务 。 本发明可以用于中断消息传递，音频流，视频流，等时事务处理，或用于跨PCI-X的多处理器架构中用于通信的高性能，低带宽控制结构。

公开(公告)号：US06247087B1

公开(公告)日：2001-06-12

申请号：US09036634

申请日：1998-03-06

Applicant: Dwight D. Riley ,  David J. Maguire

Inventor： Dwight D. Riley ,  David J. Maguire

IPC: G06F1300

CPC classification number: G06F13/4027

Abstract: The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

Abstract translation: 本发明涉及一种用于对共享共同地址的计算机系统的第一寄存器和第二寄存器的数据进行阴影化的系统和方法。 当总线代理对寄存器地址执行写入操作时，第一桥接电路的重试逻辑重试写入操作，并掩盖总线代理对总线的访问。 重试总线主机逻辑重新执行写入操作，响应于此，第二桥接电路对该重新运行写入操作进行减法解码并将数据传送到第二寄存器。 然后允许总线代理重试初始写操作，响应于此，第一桥电路对其进行重试写入操作，并将数据传送到第一寄存器。 因此，在第一和第二寄存器之间保持一致性。