公开(公告)号：US06795281B2

公开(公告)日：2004-09-21

申请号：US09963933

申请日：2001-09-25

Applicant: Lung Tran ,  Manish Sharma ,  Manoj Bhattacharyya

Inventor： Lung Tran ,  Manish Sharma ,  Manoj Bhattacharyya

IPC: H01L2984

CPC classification number: B82Y25/00 ,  G11C11/16 ,  H01F10/3277

Abstract: A memory device includes a data layer having a magnetization that can be oriented in first and second directions; and a synthetic ferrimagnet reference layer. The data and reference layers have different coercivities.

Abstract translation: 存储器件包括具有可以在第一和第二方向上定向的磁化的数据层; 和合成亚铁磁参考层。 数据和参考层具有不同的矫顽力。

公开(公告)号：US06584589B1

公开(公告)日：2003-06-24

申请号：US09498588

申请日：2000-02-04

Applicant: Frederick A. Perner ,  Kenneth J. Eldredge ,  Lung Tran

Inventor： Frederick A. Perner ,  Kenneth J. Eldredge ,  Lung Tran

IPC: G11C2900

CPC classification number: G11C29/50 ,  G11C27/02 ,  G11C29/02 ,  G11C29/44

Abstract: A collection of testing circuits are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays. The combination of testing circuits can detect MRAM array defects including: open rows, shorted memory cells, memory cells which are outside of resistance specifications, and simple read/write pattern errors. The built-in test circuits include a wired-OR circuit connecting all the rows to test for open rows and shorted memory cells. A dynamic sense circuit detects whether the resistance of memory cells is within specified limits. An exclusive-OR gate combined with global write controls is integrated into the sense amplifiers and is used to perform simple read-write pattern tests. Error data from the margin tests and the read-write tests are reported through a second wired-OR circuit. Outputs from the two wired-OR circuits and the associated row addresses are reported to the test processor or recorded into an on-chip error status table.

Abstract translation: 公开了一系列测试电路，可用于形成用于MRAM阵列的综合内置测试系统。 测试电路的组合可以检测MRAM阵列缺陷，包括：开放行，短路存储单元，超出电阻规格的存储单元，以及简单的读/写模式错误。 内置的测试电路包括连接所有行的线OR电路，以测试打开的行和短路存储单元。 动态感测电路检测存储器单元的电阻是否在规定的范围内。 与全局写入控制相结合的异或门被集成到读出放大器中，用于执行简单的读写模式测试。 来自裕度测试和读写测试的错误数据通过第二个有线电路报告。 来自两个有线OR电路和相关行地址的输出被报告给测试处理器或记录在片上错误状态表中。