公开(公告)号：US5808971A

公开(公告)日：1998-09-15

申请号：US726075

申请日：1996-10-03

Applicant: Roberto Alini ,  Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Marco Demicheli

Inventor： Roberto Alini ,  Melchiorre Bruccoleri ,  Gaetano Cosentino ,  Marco Demicheli

IPC: G11B20/14 ,  H03K17/14 ,  H03K17/28 ,  G04F37/00

CPC classification number: H03K17/14 ,  H03K17/28 ,  G11B20/1403

Abstract: A temperature-compensated high-speed timing circuit, which is particularly advantageous in read-interface circuits for disk-drive interface. The voltage on the integrating capacitor is compared against a voltage defined by the drop, on a resistor, induced by a current which is the combination of a reference current from a reference current generator with a temperature-dependent current from another current generator.

公开(公告)号：US5621358A

公开(公告)日：1997-04-15

申请号：US454924

申请日：1995-05-31

Applicant: Valerio Pisati ,  Roberto Alini ,  Rinaldo Castello ,  Gianfranco Vai

Inventor： Valerio Pisati ,  Roberto Alini ,  Rinaldo Castello ,  Gianfranco Vai

IPC: H03F3/343 ,  H03F3/45 ,  H03G1/00 ,  H03H11/24

CPC classification number: H03F3/45883 ,  H03F3/45286 ,  H03F3/45807 ,  H03G1/0023 ,  H03F2203/45648

Abstract: A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) connected between said output terminals (O1, O2) and the active load (4).Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.

Abstract translation: 包括具有至少两个输入端（I1，I2）和至少两个输出端（O1，O2）的跨导级（3）的受控增益跨导体（20），连接到 跨导级和连接在所述输出端子（O1，O2）和有源负载（4）之间的有源负载（4）的控制电路（5）。 还提供了作为跨导级（3），有源负载（4）和控制电路（5）的复制品的电路部分（10）。 该复制部分（10）具有连接到跨导体（20）的控制电路（5）的输出，以提供调整装置的DC增益所需的预定电压值（Vc）。

公开(公告)号：US5528237A

公开(公告)日：1996-06-18

申请号：US285918

申请日：1994-08-03

Applicant: David Moloney ,  Paolo Gadducci ,  Giorgio Betti ,  Roberto Alini

Inventor： David Moloney ,  Paolo Gadducci ,  Giorgio Betti ,  Roberto Alini

IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14 ,  H03M7/00

CPC classification number: H03M5/145 ,  G11B20/1426

Abstract: A decoder for decoding a serial data stream employs an extracted base clock signal, synchronous with an input, coded, serial data stream, a first fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary frequency clock signal for synthesizing a pre-decoded value, produced by a first combinative logic network, within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop. In a decoder according to the present invention, a pipelined operation is implemented by momentarily storing the bits (part of the bits handled by the decoder) that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock signal the processing, by said first combinative network, of the total n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the rising front of the output sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating speed may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

Abstract translation: 用于解码串行数据流的解码器采用提取的基本时钟信号，与输入，编码的串行数据流同步，用于对解码的输出数据流进行采样的第一分数次频率时钟信号和用于合成预 由第一组合逻辑网络产生的解码值在第二组合逻辑网络内，以产生被发送到输出采样触发器的解码值。 在根据本发明的解码器中，通过暂时存储在第二组合逻辑网络中处理的比特（由解码器处理的一部分比特）并通过预测同步基准时钟的两个完整周期来实现流水线操作 通过所述第一组合网络处理由解码器处理的总共n个比特的比特的信号。 允许两个组合逻辑网络中的每一个在输出采样时钟信号的上升沿之前的整个时钟周期内完成其解码处理。 使用相同的制造技术，因此具有相同的两个组合逻辑网络的传播延迟，最大的操作速度可以加倍。 需要有限数量的附加部件来实现本发明的流水线操作。

公开(公告)号：US5332937A

公开(公告)日：1994-07-26

申请号：US942678

申请日：1992-09-09

Applicant: Rinaldo Castello ,  Roberto Alini ,  Andrea Baschirotto ,  Gianfranco Vai

Inventor： Rinaldo Castello ,  Roberto Alini ,  Andrea Baschirotto ,  Gianfranco Vai

IPC: H03F3/45 ,  H03H11/04 ,  H03K5/24

CPC classification number: H03F3/45179 ,  H03F3/45286 ,  H03F2203/45024 ,  H03H11/0433

Abstract: A transconductor differential stage for high-frequency filters, which has a MOS differential input pair with common sources. The drain of each MOS input is connected to the emitter of an npn bipolar. These two matched bipolars have their gates connected together with the gate of a third bipolar, which is diode-connected. Two matched current sources feed the two bipolars, and a third current source feeds the third bipolar. A single controlled current sink is connected to the sources of both MOS input transistors, and also (through a resistor) to the third bipolar.

Abstract translation: 用于高频滤波器的跨导差分级，具有通用源的MOS差分输入对。 每个MOS输入的漏极连接到npn双极的发射极。 这两个匹配的双极子的栅极与第二极二极管连接的第三极的栅极连接在一起。 两个匹配的电流源馈送两个双极，第三个电流源馈送第三个双极。 单个受控电流吸收器连接到两个MOS输入晶体管的源极，并且（通过电阻器）连接到第三极。