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公开(公告)号：US5621358A
公开(公告)日：1997-04-15
申请号：US454924
申请日：1995-05-31
CPC分类号： H03F3/45883 , H03F3/45286 , H03F3/45807 , H03G1/0023 , H03F2203/45648
摘要： A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) connected between said output terminals (O1, O2) and the active load (4).Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.
摘要翻译： 包括具有至少两个输入端（I1，I2）和至少两个输出端（O1，O2）的跨导级（3）的受控增益跨导体（20），连接到 跨导级和连接在所述输出端子（O1，O2）和有源负载（4）之间的有源负载（4）的控制电路（5）。 还提供了作为跨导级（3），有源负载（4）和控制电路（5）的复制品的电路部分（10）。 该复制部分（10）具有连接到跨导体（20）的控制电路（5）的输出，以提供调整装置的DC增益所需的预定电压值（Vc）。
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公开(公告)号：US5912582A
公开(公告)日：1999-06-15
申请号：US866889
申请日：1997-05-30
CPC分类号： H03F3/72 , H03F3/45286 , H03F2203/45302 , H03F2203/45304 , H03F2203/45371 , H03F2203/45396 , H03F2203/45506
摘要： A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor. In a variant differential stage, there are also provided respective added MOS transistors connected in parallel with the MOS transistors of the input circuit portion to change the ratio W:L of each of the MOS transistors.
摘要翻译： 用于高频滤波器的BiCMOS跨导差分级包括具有信号输入的输入电路部分和具有对应于信号输入的各自的栅极端子的一对MOS晶体管。 差分级具有具有信号输出的输出电路部分和一对双极晶体管，它们以共模基极连接在共模基底上，该公共基极以共源共栅配置插入在输入端和输出端之间。 差分级包括与双极晶体管中的至少一个相关联的开关器件，以改变差分级中存在的寄生电容器之间的连接。 开关器件还具有至少一个加法双极晶体管，其以可移除的方式与相应的双极共源共栅晶体管并联连接。 在变异差分级中，还提供了与输入电路部分的MOS晶体管并联连接的各个附加的MOS晶体管，以改变每个MOS晶体管的比率W：L。
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公开(公告)号：US5430337A
公开(公告)日：1995-07-04
申请号：US105736
申请日：1993-08-12
CPC分类号： H03F1/3211 , H03F3/45076 , H03F3/45282
摘要： A transconductor stage for high-frequency filters of a type which comprises an input circuit portion having signal inputs and an output circuit portion, incorporates a pair of field-effect transistors having respective gate and source terminals in common, and has the output portion formed of a pair of bipolar transistors connected to the aforesaid field-effect transistors.
摘要翻译： 一种用于包括具有信号输入的输入电路部分和输出电路部分的类型的高频滤波器的跨导级，包括一对共同具有各自的栅极和源极端子的场效应晶体管，并且具有由 连接到上述场效应晶体管的一对双极晶体管。
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公开(公告)号：US06424172B1
公开(公告)日：2002-07-23
申请号：US09796996
申请日：2001-02-28
IPC分类号： H03K19082
CPC分类号： H03H11/0422
摘要： This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor. Thus, a released “zero” can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
摘要翻译： 本发明涉及具有可编程零点的前馈类型的电路结构，特别是用于合成时间连续滤波器。 该结构包括互连至少一个互连节点并连接在第一单元的第一信号输入和第二单元的输出端之间的一对放大单元，每个单元包括一对具有共同的导通端子并具有 其它导电端子通过相应的偏置构件分别耦合到第一电压基准。 所述结构还包括将所述第一单元的节点连接到所述输出端子并且包括具有连接到所述第一单元的节点的控制端子的晶体管，连接到所述输出端子的第一导通端子和第二导通 端子通过电容器耦合到第二参考电压。 因此，可以在极零复平面的右半平面中引入释放的“零”，以改善组增益的平坦化。
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公开(公告)号：US06359503B1
公开(公告)日：2002-03-19
申请号：US08999962
申请日：1997-08-12
IPC分类号： H03K500
CPC分类号： H03H15/00 , H02P6/21 , H03H11/0422
摘要： An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node. “Elementary cell structure for programmable time-continuous analog filters and in particular for read/write operations on magnetic supports and associated analog filter”
摘要翻译： 用于可编程时间连续模拟滤波器的基本单元结构，特别是用于在磁性支撑上的读取/写入操作中处理模拟信号的基本单元结构包括：放大器级，其设置有一对在公共电路节点中连接在一起的结构相同的跨导半电池 。 这种类型的单元级联提供了一种时间连续的模拟延迟线，其用于横向时间连续的模拟滤波器。 该滤波器包括通过乘法器节点连接到最终求和节点的相同延迟线级联。 “用于可编程时间连续模拟滤波器的基本单元结构，特别是用于磁性支持和相关模拟滤波器的读/写操作”
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公开(公告)号：US5644267A
公开(公告)日：1997-07-01
申请号：US455850
申请日：1995-05-31
CPC分类号： H03H11/0433
摘要： A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i.sub.K1, i.sub.K2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).
摘要翻译： 一种高通滤波器，特别适用于高频应用，并且包括至少一个输入端（IN）和至少一个输出端（OUT）的类型，其间被定义为传递函数（FdT），并被插入一个二次电池 包括一系列跨导级（2,3,4,5）的（18）包括连接在所述二次电池（18）的一对级（2,3）之间的可变电流（iK1，iK2）的发电机电路（29） ）和电压基准（GND）。 所述发生器允许在滤波器（20）的传递函数（FdT）中引入可编程零点。
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公开(公告)号：US5963065A
公开(公告)日：1999-10-05
申请号：US787301
申请日：1997-01-24
CPC分类号： H03F3/3077
摘要： A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).
摘要翻译： 低失调放大器具有由推挽装置中的npn晶体管和pnp晶体管构成的输出级和驱动级。 后者包括电流镜电路，其在其输入支路中具有与第一恒定电流发生器串联的pnp晶体管，并且在其输出支路中具有npn晶体管，以及两个互补双极晶体管，其中集电极连接到输出端 端子和基极连接到放大器的输入端子。 驱动器级的pnp晶体管的发射极通过第二恒流发生器连接到电源的正极端子，并连接到输出级的npn晶体管的基极，驱动器级的npn晶体管的发射极 通过电流镜电路的输出支路的npn晶体管和输出级的pnp晶体管的基极连接到电源的负极。 放大器具有非常低或零偏移（Vos = Vout-Vin）。
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公开(公告)号：US07061300B2
公开(公告)日：2006-06-13
申请号：US09797204
申请日：2001-02-27
IPC分类号： G05F1/10
CPC分类号： G06G7/163 , H03D7/1408 , H03D7/1433 , H03D7/1491 , H03D2200/0086
摘要： The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.
摘要翻译： 本发明涉及一种低电源模拟乘法器，其包括一对差分单元，每个单元包括一对具有耦合发射极的双极晶体管。 每个单元的第一晶体管在其基极端子上接收输入信号，并且其集电极端子通过偏置构件耦合到第一电压基准。 有利地，每个单元的第二晶体管是二极管配置，并且这些单元在对应于每对中的第二晶体管的基极端子的公共节点处互连。 该乘法器可以提供非常低的电压，并且仍然表现出高的运行速率以及降低的输出信号的谐波失真，即使高峰值幅度高于600 mV的输入信号也是如此。
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9.发明授权
公开(公告)号：US5821829A
公开(公告)日：1998-10-13
申请号：US810032
申请日：1997-03-04
CPC分类号： H03L7/0805 , H03L7/099
摘要： The system includes various circuit units each having a capacitor and a charging circuit for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop which uses one of the circuit units as an adjustable oscillator, and current transducer means which regulates the charging currents of the capacitors of the circuit units in dependence on the regulated charging current of the capacitor of the oscillator, or the error current of the PLL loop.
摘要翻译： 该系统包括各自具有电容器的电路单元和用于根据充电电流和电容器的电容之间的比率（I / C）定义量的充电电路。 为了自动补偿由于集成电路制造过程的参数波动引起的实际电容与标称电容的偏差，系统具有使用电路单元之一作为可调谐振荡器的锁相环，以及 电流传感器装置，其根据振荡器的电容器的调节的充电电流或PLL环路的误差电流来调节电路单元的电容器的充电电流。
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10.发明授权Variable-gain multistage amplifier with broad bandwidth and reduced phase variations 有权可变增益多级放大器，带宽宽，相位变化减小公开(公告)号：US06246289B1
公开(公告)日：2001-06-12
申请号：US09507562
申请日：2000-02-18
IPC分类号： H03F345
CPC分类号： H03G1/0023
摘要： A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors. The amplifier further includes two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.
摘要翻译： 一种具有宽带宽和相位变化较小的可编程增益多级放大器，具有由第一电流源偏置的差分输入级，馈送差分电压信号，该级连接到阴极端子连接的一对二极管 到由双极晶体管的集电极端子提供的由第二电流源偏置并且其中集电极端子连接到负载电阻器的各个双极晶体管，放大器的差分输出被提供。 放大器还包括两个电路分支，每个电路分支由双极晶体管和第三电流源构成，第三电流源分别连接到双极晶体管的集电极端子和发射极端子，其中基极端子接收差分电压信号 并且集电极端子连接到两个二极管中的相应一个的阴极端子，电路分支通过一对电容器相互连接。
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