公开(公告)号：US07596733B2

公开(公告)日：2009-09-29

申请号：US12178517

申请日：2008-07-23

Applicant: Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic J. Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic J. Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

IPC: G01R31/28

CPC classification number: G01R31/318572 ,  G01R31/318536

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract translation: 提供了低开销动态可重配置的共享扫描测试架构。 该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。 重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

公开(公告)号：US20080294955A1

公开(公告)日：2008-11-27

申请号：US12178504

申请日：2008-07-23

Applicant: Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318572 ,  G01R31/318536

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract translation: 提供了低开销动态可重配置的共享扫描测试架构。 该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。 重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

公开(公告)号：US07418640B2

公开(公告)日：2008-08-26

申请号：US10856105

申请日：2004-05-28

Applicant: Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318572 ,  G01R31/318536

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract translation: 提供了低开销动态可重配置的共享扫描测试架构。 该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。 重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

公开(公告)号：US20050268190A1

公开(公告)日：2005-12-01

申请号：US10856105

申请日：2004-05-28

Applicant: Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas Williams

Inventor： Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas Williams

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318572 ,  G01R31/318536

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract translation: 提供了低开销动态可重配置的共享扫描测试架构。 该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。 重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

公开(公告)号：US06434733B1

公开(公告)日：2002-08-13

申请号：US09275502

申请日：1999-03-24

Applicant: Suryanarayana Duggirala ,  Rohit Kapur ,  Thomas W. Williams

Inventor： Suryanarayana Duggirala ,  Rohit Kapur ,  Thomas W. Williams

IPC: G06F1750

CPC classification number: G01R31/318594 ,  G01R31/318536 ,  G01R31/318583

Abstract: A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of re-orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. According to one embodiment of the present invention, the scan-chain is partitioned into a number of different sets based the respective clock domains, edge sensitivity types skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to the place-and-route processes to be used as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set. The present invention thereby allows a better designed integrated circuit to be designed and fabricated.

Abstract translation: 用于集成电路设计的测试模式电路的布局规划的过程和系统。 该新颖方法包括以下步骤：将网表的扫描链分成可重排序扫描单元的集合。 网表被传递到布局处理，其中扫描链的扫描单元基于这些集合被重新排序。 根据本发明的一个实施例，扫描链基于相应的时钟域，边缘灵敏度类型偏差容限水平，周围锥形逻辑，可重新配置和扫描单元的同时输出切换要求被划分成多个不同的集合。 然后将代表结果集的数据提供给用于重新排序限制的地点和路由过程。 特别地，重新排序限制限制了不同组之间的扫描单元的重排。 然而，放置和布线过程不限于重新排列同一集合内的扫描单元的顺序。 因此，本发明允许设计和制造更好设计的集成电路。