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    Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry
    1.
    发明授权
    Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry 有权
    测试架构包括循环缓存链，选择性旁路扫描链段和阻塞电路

    公开(公告)号：US08479067B2

    公开(公告)日：2013-07-02

    申请号：US12762048

    申请日：2010-04-16

    Applicant: Anshuman Chandra ,  Jyotirmoy Saikia ,  Rohit Kapur

    Inventor： Anshuman Chandra ,  Jyotirmoy Saikia ,  Rohit Kapur

    IPC: G01R31/28

    CPC classification number: G01R31/318536 ,  G01R31/318547

    Abstract: A test architecture adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values. The test architecture can include control logic for selecting between a linear mode and a cyclical mode. In the linear mode, only top level scan inputs are mapped to the scan chains. In the cyclical mode, outputs of the plurality of cyclical cache chains and top level scan inputs are mapped to the scan chains.

    Abstract translation: 测试架构通过为设计的扫描链提供的一组测试图案使用一个或多个循环高速缓存链来增加最小面积开销并增加编码带宽。 与扫描链相关联的多路复用器可用于绕过包括未知值的扫描链段。 阻塞电路可以编程为完全阻止一个或多个扫描链，包括未知值。 测试架构可以包括用于在线性模式和循环模式之间进行选择的控制逻辑。 在线性模式下，只有顶级扫描输入被映射到扫描链。 在循环模式中，多个循环高速缓存链和顶层扫描输入的输出被映射到扫描链。

    Systemic Diagnostics For Increasing Wafer Yield
    2.
    发明申请
    Systemic Diagnostics For Increasing Wafer Yield 有权
    系统诊断用于提高晶圆产量

    公开(公告)号：US20110040528A1

    公开(公告)日：2011-02-17

    申请号：US12854120

    申请日：2010-08-10

    Applicant: Rohit Kapur ,  Mallika Kapur ,  Maya Kapur

    Inventor： Rohit Kapur ,  Mallika Kapur ,  Maya Kapur

    IPC: G06F15/00

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of performing systemic diagnostics for a wafer includes selecting a design for manufacturability (DFM) rule for analysis. For each IC chip on the wafer, two sets of IC features adjacent the rule can be extracted based on the chip's layout design. Upconverted diagnostics can be run to generate computed numbers associated with combination categories for each set. Zonal analysis can be run on the two sets using the computed numbers to derive metrics for the two sets. A report can be generated based on the zonal analysis.

    Abstract translation: 为晶片执行系统诊断的方法包括选择用于分析的可制造性（DFM）规则的设计。 对于晶片上的每个IC芯片，可以基于芯片的布局设计提取与规则相邻的两组IC特征。 可以运行上转换的诊断程序，以生成与每个组合的组合类别相关联的计算数字。 可以使用计算的数字在两组上运行区域分析，以得出两组的度量。 可以根据区域分析生成报告。

    Scan compression circuit and method of design therefor
    5.
    发明授权
    Scan compression circuit and method of design therefor 有权
    扫描压缩电路及其设计方法

    公开(公告)号：US07814444B2

    公开(公告)日：2010-10-12

    申请号：US11807119

    申请日：2007-05-25

    Applicant: Peter Wohl ,  John A. Waicukauski ,  Sanjay Ramnath ,  Rohit Kapur ,  Thomas W. Williams

    Inventor： Peter Wohl ,  John A. Waicukauski ,  Sanjay Ramnath ,  Rohit Kapur ,  Thomas W. Williams

    IPC: G06F17/50

    CPC classification number: H03M7/30 ,  G06F17/505 ,  G06F2217/14

    Abstract: A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

    Abstract translation: 基于扫描的电路包括通过多个观察逻辑实现的选择器。 每个观察逻辑耦合到扫描链以接收要提供给组合式压缩机的数据。 每个观察逻辑还耦合到组合压缩机的相应组输入线中的单个输入线，以选择性地从耦合的扫描链提供数据。 每个观察逻辑可以耦合到相应组中的附加输入线（如果存在）。 在（a）透明模式中，选择器可以在每个移位的基础上操作，其中数据被提供给所有输入线，并且（b）几个直接模式，其中来自仅一个扫描链的数据仅在每个压缩器输出处被提供而不重叠。

    System and method for time slicing deterministic patterns for reseeding in logic built-in self-test
    7.
    发明授权
    System and method for time slicing deterministic patterns for reseeding in logic built-in self-test 有权
    用于时间分片的系统和方法用于逻辑内置自检中的重新采样的确定性模式

    公开(公告)号：US06807646B1

    公开(公告)日：2004-10-19

    申请号：US10091614

    申请日：2002-03-04

    Applicant: Thomas W. Williams ,  Peter Wohl ,  John A. Waicukauski ,  Rohit Kapur

    Inventor： Thomas W. Williams ,  Peter Wohl ,  John A. Waicukauski ,  Rohit Kapur

    IPC: G06F1100

    CPC classification number: G01R31/318307 ,  G01R31/318328

    Abstract: A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern is divided into a number of segments, with each segment having a specific number of “care” bits. The number of shifts required to fill a segment using a particular seed is stored along with the seed as a seed lifetime. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the lifetime of the seed. The seed lifetimes may have different values, and multiple seeds may be used in the generation of a single test pattern, or a single seed may be used to generate care bits of multiple test patterns.

    Abstract translation: 用于在逻辑内置自检（BIST）中时间切片确定性模式以重新进给的系统和方法。 线性反馈移位寄存器（LFSR）和关联的一组通道的已知属性与期望的确定性测试模式结合使用以创建一个或多个可由LFSR用于生成测试模式的种子。 测试图案被分成多个段，每个段具有特定数量的“关心”位。 使用特定种子填充段所需的班次数与种子一起作为种子生存期一起存储。 在测试期间，通过将种子加载到LFSR中并根据种子的寿命循环LFSR来产生每个确定性测试模式。 种子寿命可以具有不同的值，并且可以在生成单个测试图案时使用多个种子，或者可以使用单个种子来生成多个测试图案的护理位。

    Dynamic scan chains and test pattern generation methodologies therefor
    8.
    发明授权
    Dynamic scan chains and test pattern generation methodologies therefor 有权
    动态扫描链和测试模式生成方法

    公开(公告)号：US06615380B1

    公开(公告)日：2003-09-02

    申请号：US09469729

    申请日：1999-12-21

    Applicant: Rohit Kapur ,  Denis Martin ,  Thomas W. Williams

    Inventor： Rohit Kapur ,  Denis Martin ,  Thomas W. Williams

    IPC: G06F1100

    CPC classification number: G06F11/263 ,  G01R31/318544 ,  G01R31/318547 ,  G06F11/267

    Abstract: According to the present invention, during scan conversion, non-scan memory cells of a circuit design are replaced with scan cells to form a scan chain. The scan chain is transformed by the test synthesis tool of the present invention into dynamic scan chains with the addition of reconfiguration circuitry. The reconfiguration circuitry partitions the scan chain into multiple segments and enables each segment to be selectively “bypassed” (or deactivated) during test application. Shorter test patterns that are only pertinent to one or more segments are necessary, resulting in a reduction in overall test data volume and test application time. The present invention also provides a modified ATPG technique for generating test patterns for the dynamic scan chains.

    Abstract translation: 根据本发明，在扫描转换期间，将电路设计的非扫描存储单元替换为扫描单元以形成扫描链。 扫描链由本发明的测试合成工具转化成动态扫描链，并添加了重构电路。 重新配置电路将扫描链分成多个段，并使测试应用中的每个段选择性地“旁路”（或停用）。 与一个或多个部分相关的更短的测试模式是必要的，导致整体测试数据量和测试应用时间的减少。 本发明还提供了一种用于生成动态扫描链的测试模式的改进的ATPG技术。

    Method for placement-based scan-in and scan-out ports selection
    9.
    发明授权
    Method for placement-based scan-in and scan-out ports selection 有权
    基于布局的扫描和扫描端口选择方法

    公开(公告)号：US06405355B1

    公开(公告)日：2002-06-11

    申请号：US09283095

    申请日：1999-03-31

    Applicant: Suryanarayana Duggirala ,  Rohit Kapur ,  Thomas W. Williams

    Inventor： Suryanarayana Duggirala ,  Rohit Kapur ,  Thomas W. Williams

    IPC: G01R3128

    CPC classification number: G01R31/318536 ,  G01R31/318583 ,  G01R31/318594

    Abstract: A computer implemented method of constructing a scan chain. According to the present invention, scan cells are inserted into a netlist description of an integrated circuit design and are coupled serially together to form a scan chain. The resulting netlist is then passed to layout processes where the cells of the integrated circuit design are automatically placed and routed. The layout processes are performed without regard to any predetermined constraints designating any particular functional pins of the netlist design as scan-in or scan-out ports for the scan chain. After the cells are placed, a first functional pin is selected as the scan-in port and a second functional pin is selected as the scan-out port according to cell placement information. In particular, the functional pin that is closest to the leading scan cell is selected as the scan-in port. The functional pin that is closest to the last scan cell is selected as the scan-out port for the scan chain. Scan-in functionalities are then added to the first functional pin and scan-out functionalities are added to the second functional pin. The present invention thereby improves cell placement and wire routability, and allows a better integrated circuit to be designed and fabricated.

    Abstract translation: 构建扫描链的计算机实现方法。 根据本发明，将扫描单元插入到集成电路设计的网表描述中，并且串联耦合以形成扫描链。 所得到的网表然后被传递到布局处理，其中集成电路设计的单元被自动放置和布线。 执行布局处理而不考虑将网表设计的任何特定功能引脚指定为用于扫描链的扫描输入或扫描输出端口的任何预定约束。 放置单元后，选择第一个功能引脚作为扫描输入端口，并根据单元格放置信息选择第二个功能引脚作为扫描输出端口。 特别地，选择最靠近前导扫描单元的功能引脚作为扫描入口。 选择最接近最后一个扫描单元的功能引脚作为扫描链的扫描输出端口。 然后将扫描功能添加到第一个功能引脚，并将扫描功能添加到第二个功能引脚。 本发明因此改善了电池放置和电线布线性，并且可以设计和制造更好的集成电路。

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