公开(公告)号：US06996596B1

公开(公告)日：2006-02-07

申请号：US09577238

申请日：2000-05-23

Applicant: Ying-wai Ho ,  Xing Yu Jiang

Inventor： Ying-wai Ho ,  Xing Yu Jiang

IPC: G06F7/38

CPC classification number: G06F7/483 ,  G06F7/49963

Abstract: Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an operand processing section and an operand flush section. For each floating-point operation, the operand processing section receives and processes one or more input operands to provide a preliminary result. The operand flush section determines whether the preliminary result falls within one of a number of ranges of values and sets the preliminary result to one of a number of set values if the preliminary result falls within one of the ranges. In a specific implementation, a first range of values is defined to include values greater than zero and less than half of a minimum normalized number (i.e., 0

Abstract translation: 浮点单元（FPU）和处理器具有“齐平到最近”操作模式，提供了比常规“冲洗到零”模式提高的精度。 FPU或处理器包括操作数处理部分和操作数清零部分。 对于每个浮点运算，操作数处理部分接收并处理一个或多个输入操作数以提供初步结果。 操作数刷新部分确定初步结果是否在数值范围内的一个范围内，如果初步结果在一个范围内，则将初步结果设置为多个设定值之一。 在具体实现中，第一范围的值被定义为包括大于零且小于最小归一化数的一半的值（即，0 <| Y | <+ A / 2） 值的第二范围被定义为包括等于或大于+ a分钟/小于+小于+分钟的值（即， 2 <= | Y | 分），并且如果初步结果落在第一范围内并将其设置为零，则为+ a分钟或-a _{min （取决于符号位），如果它落在第二个范围内。}

公开(公告)号：US20050213610A1

公开(公告)日：2005-09-29

申请号：US10930233

申请日：2004-08-31

Applicant: Tai-Xing Yu ,  Hong-Chi Hsu ,  Teng-Yi Huang ,  Ting-Kai Hung ,  Li-Chung Chuang

Inventor： Tai-Xing Yu ,  Hong-Chi Hsu ,  Teng-Yi Huang ,  Ting-Kai Hung ,  Li-Chung Chuang

IPC: H04L12/66 ,  H04L29/06 ,  H04M7/00

CPC classification number: H04M7/0072 ,  H04L29/06027 ,  H04L65/80 ,  H04M7/006

Abstract: A compressor/decompressor (Codec) selecting apparatus includes a performance analyzer, a training server, a storage unit, and a selecting unit. The performance analyzer analyzes the performance of the current internet communication system, and outputs environmental parameters accordingly. The training server obtains learning data corresponding to a hyperplane according to training samples. The storage unit stores the learning data and the related parameters. The selecting unit does a functional analysis according to the environmental parameters and the learning data in order to select the Codec suitable for the current internet communication system.

Abstract translation: 压缩器/解压缩器（编解码器）选择装置包括性能分析器，训练服务器，存储单元和选择单元。 性能分析器分析当前互联网通信系统的性能，并相应地输出环境参数。 训练服务器根据训练样本获取对应于超平面的学习数据。 存储单元存储学习数据和相关参数。 选择单元根据环境参数和学习数据进行功能分析，以选择适合于当前互联网通信系统的编解码器。

公开(公告)号：US06218234B1

公开(公告)日：2001-04-17

申请号：US09298934

申请日：1999-04-26

Applicant: Xing Yu ,  Shao Kai

Inventor： Xing Yu ,  Shao Kai

IPC: H01L218242

CPC classification number: H01L27/0629

Abstract: A method for integrating the dual gate and double poly capacitor processes to fabricate an analog capacitor integrated circuit device is described. An isolation region is provided separating a first active area from a second active area in a semiconductor substrate. A first gate oxide layer is formed overlying the semiconductor substrate in both active areas. A first polysilicon layer is deposited overlying the first gate oxide layer and the isolation region. An capacitor dielectric layer comprising an oxide layer and a nitride layer is deposited overlying the first polysilicon layer. The capacitor dielectric layer and first polysilicon layer are etched away where they are not covered by a mask to form a first polysilicon gate electrode in the first area and a polysilicon capacitor bottom plate and overlying capacitor dielectric overlying the isolation region. The first gate oxide layer is removed in the second area and a thinner second gate oxide layer is formed in the second area. A second polysilicon layer is deposited overlying the second gate oxide layer, bottom capacitor plate and capacitor dielectric, and the first polysilicon gate electrode. The second polysilicon layer is etched away where it is not covered by a mask to form a second polysilicon gate electrode in the second area and to form a top capacitor plate overlying the bottom capacitor plate having the capacitor dielectric layer therebetween.

Abstract translation: 描述了一种用于整合双栅极和双重多晶硅电容器工艺以制造模拟电容器集成电路器件的方法。 提供了隔离区域，其将第一有源区域与半导体衬底中的第二有源区域分开。 在两个有源区域中形成覆盖半导体衬底的第一栅极氧化物层。 第一多晶硅层沉积在第一栅极氧化物层和隔离区上。 包括氧化物层和氮化物层的电容器电介质层沉积在第一多晶硅层上。 电容器电介质层和第一多晶硅层被蚀刻掉，其中它们不被掩模覆盖，以在第一区域中形成第一多晶硅栅电极，并且在多晶硅电容器底板和覆盖隔离区域的上覆电容器电介质上。 在第二区域中去除第一栅极氧化物层，并且在第二区域中形成更薄的第二栅极氧化物层。 沉积第二多晶硅层，覆盖第二栅极氧化物层，底部电容器板和电容器电介质，以及第一多晶硅栅电极。 第二多晶硅层被蚀刻掉，其未被掩模覆盖，以在第二区域中形成第二多晶硅栅电极，并且形成覆盖在其间的电容器电介质层的底部电容器板的顶部电容器板。