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    Dual gate and double poly capacitor analog process integration
    1.
    发明授权
    Dual gate and double poly capacitor analog process integration 失效
    双门和双电容模拟过程集成

    公开(公告)号：US06218234B1

    公开(公告)日：2001-04-17

    申请号：US09298934

    申请日：1999-04-26

    Applicant: Xing Yu ,  Shao Kai

    Inventor： Xing Yu ,  Shao Kai

    IPC: H01L218242

    CPC classification number: H01L27/0629

    Abstract: A method for integrating the dual gate and double poly capacitor processes to fabricate an analog capacitor integrated circuit device is described. An isolation region is provided separating a first active area from a second active area in a semiconductor substrate. A first gate oxide layer is formed overlying the semiconductor substrate in both active areas. A first polysilicon layer is deposited overlying the first gate oxide layer and the isolation region. An capacitor dielectric layer comprising an oxide layer and a nitride layer is deposited overlying the first polysilicon layer. The capacitor dielectric layer and first polysilicon layer are etched away where they are not covered by a mask to form a first polysilicon gate electrode in the first area and a polysilicon capacitor bottom plate and overlying capacitor dielectric overlying the isolation region. The first gate oxide layer is removed in the second area and a thinner second gate oxide layer is formed in the second area. A second polysilicon layer is deposited overlying the second gate oxide layer, bottom capacitor plate and capacitor dielectric, and the first polysilicon gate electrode. The second polysilicon layer is etched away where it is not covered by a mask to form a second polysilicon gate electrode in the second area and to form a top capacitor plate overlying the bottom capacitor plate having the capacitor dielectric layer therebetween.

    Abstract translation: 描述了一种用于整合双栅极和双重多晶硅电容器工艺以制造模拟电容器集成电路器件的方法。 提供了隔离区域，其将第一有源区域与半导体衬底中的第二有源区域分开。 在两个有源区域中形成覆盖半导体衬底的第一栅极氧化物层。 第一多晶硅层沉积在第一栅极氧化物层和隔离区上。 包括氧化物层和氮化物层的电容器电介质层沉积在第一多晶硅层上。 电容器电介质层和第一多晶硅层被蚀刻掉，其中它们不被掩模覆盖，以在第一区域中形成第一多晶硅栅电极，并且在多晶硅电容器底板和覆盖隔离区域的上覆电容器电介质上。 在第二区域中去除第一栅极氧化物层，并且在第二区域中形成更薄的第二栅极氧化物层。 沉积第二多晶硅层，覆盖第二栅极氧化物层，底部电容器板和电容器电介质，以及第一多晶硅栅电极。 第二多晶硅层被蚀刻掉，其未被掩模覆盖，以在第二区域中形成第二多晶硅栅电极，并且形成覆盖在其间的电容器电介质层的底部电容器板的顶部电容器板。

    Bistable liquid crystal device
    2.
    发明申请
    Bistable liquid crystal device 有权
    双稳态液晶装置

    公开(公告)号：US20070024782A1

    公开(公告)日：2007-02-01

    申请号：US10572086

    申请日：2004-10-18

    Applicant: Hoi-Sing Kwok ,  Xing Yu

    Inventor： Hoi-Sing Kwok ,  Xing Yu

    IPC: G02F1/1337 ,  G02F1/141

    CPC classification number: G02F1/1337 ,  G02F1/134363 ,  G02F1/1391 ,  G02F1/1392 ,  G02F1/1396 ,  G02F1/1397 ,  G02F2001/133746

    Abstract: This invention provides a bistable liquid crystal device. The bistable liquid crystal device includes a first substrate having thereon a first conductive layer and a first alignment layer, a second substrate having thereon a second conductive layer and a second alignment layer; and a liquid crystal layer sandwiched between the first and second alignment layers. The first alignment layer induces a first pretilt angle θ1 in the range of 20°-65° between the liquid crystal layer in contact with the first alignment layer. The second alignment layer induces a second pretilt angle θ2 in the range of 20°-65° between the liquid crystal layer in contact with the second alignment layer. The liquid crystal layer is capable of maintaining a stable bend state or a stable splay state at zero bias voltage and is switchable between the stable bend state and the stable splay state when a switching energy is applied in operation to the liquid crystal layer.

    Abstract translation: 本发明提供一种双稳态液晶装置。 双稳态液晶装置包括其上具有第一导电层和第一取向层的第一基板，其上具有第二导电层和第二取向层的第二基板; 夹在第一和第二取向层之间的液晶层。 第一取向层在与第一取向层接触的液晶层之间引发在20°-65°范围内的第一预倾角θ1。 第二取向层在与第二取向层接触的液晶层之间引起在20°-65°范围内的第二预倾角θ2。 液晶层能够在零偏压下保持稳定的弯曲状态或稳定的喷射状态，并且当在液晶层中施加开关能量时，可在稳定的弯曲状态和稳定的喷射状态之间切换。

    Method of fabrication of a raised source/drain transistor
    4.
    发明授权
    Method of fabrication of a raised source/drain transistor 有权
    凸起源极/漏极晶体管的制造方法

    公开(公告)号：US6100161A

    公开(公告)日：2000-08-08

    申请号：US442494

    申请日：1999-11-18

    Applicant: Xing Yu ,  Ying Keung Leung ,  Hong Yang ,  Shyue Fong Quek

    Inventor： Xing Yu ,  Ying Keung Leung ,  Hong Yang ,  Shyue Fong Quek

    IPC: H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/4763

    CPC classification number: H01L29/66606 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

    Abstract: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pad oxide portion. A pad oxide layer is deposited over the polysilicon layer. Shallow isolation trench regions are formed on either side of the active area. The pad oxide layer is removed. The polysilicon layer is etched and removed over the pad oxide portion leaving polysilicon portions between the pad oxide portion and the shallow isolation trench regions. The pad oxide portion is replaced with a gate oxide portion. A gate conductor, having exposed side walls, is formed over the gate oxide portion and between the polysilicon portions. Sidewall spacers are formed on the exposed side walls of the gate conductor with the sidewall spacers contacting the polysilicon portions. Source/drain regions are formed in the active area under the sidewall spacers and under the polysilicon portions. A salicide portion is formed over the gate conductor and salicide portions are formed over the polysilicon portions, whereby the formation of the salicide layers over the polysilicon portions consumes a portion of the polysilicon portions leaving the remainder of the polysilicon layers to form shallow source/drain junctions underneath the polysilicon portion salicide portions.

    Abstract translation: 一种制造晶体管的方法，包括以下步骤。 提供了在有源区内具有衬垫氧化物部分的硅半导体衬底。 多晶硅层沉积在硅半导体衬底上并在衬垫氧化物部分上方。 在多晶硅层上沉积焊盘氧化物层。 在有源区域的两侧形成浅的隔离沟槽区域。 去除衬垫氧化物层。 在衬垫氧化物部分上蚀刻并除去多晶硅层，留下衬垫氧化物部分和浅隔离沟槽区域之间的多晶硅部分。 焊盘氧化物部分被栅氧化物部分代替。 具有暴露的侧壁的栅极导体形成在栅极氧化物部分上方和多晶硅部分之间。 侧壁间隔件形成在栅极导体的暴露的侧壁上，其中侧壁间隔件与多晶硅部分接触。 源极/漏极区域形成在侧壁间隔下方的有源区域和多晶硅部分下方。 在栅极导体上形成自对准硅化物部分，并且在多晶硅部分上形成自对准硅化物部分，由此在多晶硅部分上形成硅化物层消耗部分多晶硅部分留下剩余的多晶硅层以形成浅的源极/漏极 在多晶硅部分自对准硅化物部分下方的结。

    Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers
    5.
    发明授权
    Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers 有权
    用于形成具有位于L形间隔物下方的源极/漏极延伸区域的MOSFET器件的方法

    公开(公告)号：US06455384B2

    公开(公告)日：2002-09-24

    申请号：US09972645

    申请日：2001-10-09

    Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

    Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

    IPC: H01L21336

    CPC classification number: H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

    Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

    Abstract translation: 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

    Method to form CoSi.sub.2 on shallow junction by Si implantation
    6.
    发明授权
    Method to form CoSi.sub.2 on shallow junction by Si implantation 有权
    通过Si注入在浅结上形成CoSi2的方法

    公开(公告)号：US6096647A

    公开(公告)日：2000-08-01

    申请号：US425311

    申请日：1999-10-25

    Applicant: Hong Yang ,  Xing Yu ,  Ying Keung Leung

    Inventor： Hong Yang ,  Xing Yu ,  Ying Keung Leung

    IPC: H01L21/285 ,  H01L21/44

    CPC classification number: H01L21/28518

    Abstract: A new method for forming a cobalt disilicide film on shallow junctions with reduced silicon consumption in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the semiconductor substrate and subjected to a first rapid thermal process whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer is removed. A dielectric layer is deposited overlying the substrate and the cobalt monosilicide layer. Silicon ions are implanted through the dielectric layer into the cobalt monosilicide layer. The substrate is subjected to a second rapid thermal process whereby the cobalt monosilicide is transformed to cobalt disilicide wherein the silicon ions implanted into the cobalt monosilicide layer act as a main (not sole) silicon source for the transformation to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

    Abstract translation: 描述了在制造集成电路中减少硅消耗的浅结上形成二硅化硅膜的新方法。 提供具有要被硅化的硅区域的半导体衬底。 将钴层沉积在半导体衬底上并进行第一快速热处理，由此将钴转化为一钴硅酸盐，其中它覆盖在硅区域上，并且其中不覆盖硅区域的钴是未反应的。 去除未反应的钴层。 沉积在衬底和单硅化钴层上的电介质层。 通过介电层将硅离子注入到单硅化钴层中。 对衬底进行第二快速热处理，由此将一价硅酸钴转化为二硅化钴，其中注入到一钴硅化物层中的硅离子用作主要（非唯一的）硅源，以完成二硅化硅膜的形成 在制造集成电路。

    Method for forming a raised source and drain without using selective epitaxial growth
    7.
    发明授权
    Method for forming a raised source and drain without using selective epitaxial growth 有权
    在不使用选择性外延生长的情况下形成升高的源极和漏极的方法

    公开(公告)号：US06090691A

    公开(公告)日：2000-07-18

    申请号：US439366

    申请日：1999-11-15

    Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

    Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

    IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/22

    CPC classification number: H01L29/66492 ,  H01L21/823814 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L21/2255 ,  H01L29/665

    Abstract: A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

    Abstract translation: 一种用于在不使用选择性外延硅生长的情况下形成隆起的源极和漏极结构的方法。 提供具有被介电结构覆盖的一个或多个栅极区域的半导体衬底。 掺杂的多晶硅结构与每一侧上的电介质结构相邻，并且与来自CMP工艺的电介质结构共面。 去除第一电介质结构以形成栅极开口，并且在栅极开口的底部和侧壁上形成衬里氧化物层。 在栅极开口的侧壁上的衬垫氧化物层上形成介质间隔物，并且从栅极开口的底部和掺杂的多晶硅结构上方移除衬里氧化物层。 通过从掺杂多晶硅层扩散杂质离子，在半导体衬底中形成源区和漏区。 在半导体结构上形成栅极氧化物层和栅极多晶硅层，并且平坦化栅极多晶硅层以形成栅电极。 在关键步骤中，去除电介质间隔物以形成间隔开口，并通过间隔开孔注入杂质离子并退火以形成源极和漏极延伸部分。 电介质间隔物被重整，并且在掺杂多晶硅结构和栅电极上形成自对准的硅化物层。 或者，可以在去除电介质间隔物和注入离子以形成源极和漏极延伸部之前形成自对准硅化物层。

    SYSTEM AND METHOD FOR ESTIMATING POTENTIAL UNIQUE ONLINE USERS AN ADVERTISEMENT CAN REACH
    8.
    发明申请
    SYSTEM AND METHOD FOR ESTIMATING POTENTIAL UNIQUE ONLINE USERS AN ADVERTISEMENT CAN REACH 有权
    用于估计潜在的在线用户的广告系统和方法

    公开(公告)号：US20150193811A1

    公开(公告)日：2015-07-09

    申请号：US13246609

    申请日：2011-09-27

    Applicant: Ming Lei ,  Renjie Jiang ,  Kenneth R. Alton ,  Varun Chirravuri ,  Russell W. Quong ,  Abhinay Sharma ,  Oren E. Zamir ,  Xing Yu ,  Zhengzhu Feng

    Inventor： Ming Lei ,  Renjie Jiang ,  Kenneth R. Alton ,  Varun Chirravuri ,  Russell W. Quong ,  Abhinay Sharma ,  Oren E. Zamir ,  Xing Yu ,  Zhengzhu Feng

    IPC: G06Q30/02

    CPC classification number: G06Q30/0242 ,  G06Q30/0249 ,  G06Q30/0275

    Abstract: Methods, systems, and computer programs encoded on a computer storage medium include receiving, from an advertiser, advertisement criteria associated with an advertisement, the advertisement criteria comprising a first set of criteria and a budget and/or a bid, the advertisement criteria to be used in advertisement auctions for which the advertisement is to be considered for display to users performing online actions; determining a number of users for whom the advertisement was a candidate to be shown based on the first set of criteria associated with the advertisement, but to whom the advertisement was not shown based on the budget and/or bid of the advertisement during a particular period of time; and providing, in a report, information relating to the number of users.

    Abstract translation: 在计算机存储介质上编码的方法，系统和计算机程序包括从广告商接收与广告相关联的广告标准，所述广告标准包括第一组标准和预算和/或投标，所述广告标准为 用于广告拍卖的广告拍卖，广告被考虑用于显示给执行在线动作的用户; 基于与广告相关联的第一组标准来确定广告是候选人的广告的用户数量，但是在特定时段期间基于广告的预算和/或投标而不向广告者显示广告的用户数量 的时间 并且在报告中提供与用户数量有关的信息。

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