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公开(公告)号：US20080111176A1
公开(公告)日：2008-05-15
申请号：US11560126
申请日：2006-11-15
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译： 公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。 电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。 通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。 根据每个通道区域中的电导率，电容器将呈现不同的电容值。
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公开(公告)号：US07194707B2
公开(公告)日：2007-03-20
申请号：US10711431
申请日：2004-09-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L24/06 , H01L2224/05554 , H01L2924/1305 , H01L2924/14 , H01L2924/00
摘要： Chip area corresponding to unnecessary I/O cell sites is recovered and made usable for additional core cells and power connections by grouping I/O cells into I/O kernels of contiguous I/O cells having power connections independent of other I/O kernels and depopulating I/O cell sites in accordance with areas corresponding to I/O kernels. Since I/O kernels have dedicated power connections, no power busses are present in the depopulated I/O cell sites which can then be freely use for additional core cells, power connections or the like. This technique also allows selection of a chip of minimum required area to be determined prior to design of chip layout.
摘要翻译： 通过将I / O单元分组成具有独立于其它I / O内核的电源连接的连续I / O单元的I / O内核，可以恢复对应于不需要的I / O单元位置的芯片区域并使其可用于附加核心单元和电源连接， 根据对应于I / O内核的区域，减少I / O单元位置。 由于I / O内核具有专用电源连接，所以在经过缩减的I / O单元站点中不存在功率总线，然后可以自由地使用电源总线用于其他核心单元，电源连接等。 该技术还允许在设计芯片布局之前选择要确定的最小所需区域的芯片。
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43.发明授权公开(公告)号：US07138701B2
公开(公告)日：2006-11-21
申请号：US10605483
申请日：2003-10-02
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.
摘要翻译： 一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。 半导体器件优选为二极管结型。
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公开(公告)号：US07088131B1
公开(公告)日：2006-08-08
申请号：US11161334
申请日：2005-07-29
IPC分类号： H03K19/003 , G05F3/02 , H01L21/00
CPC分类号： H03K19/0016 , G11C5/14 , G11C7/02 , H03K19/0013 , H03K19/00315
摘要： Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection to a disable signal source, and an island voltage net for supplying voltage to devices on the island. A power gate control circuit is responsive to the disable signal source for generating a test signal for selectively turning off the FET power gate as the disable signal source goes to a logical ‘1’, and for turning on the FET power gate as said disable source goes to a logical ‘0’. The FET power gate is responsive to the disable signal source being off for connecting the island voltage net to the global voltage source. A turn on finisher circuit is responsive to the disable signal transitioning to on and to the test signal for holding the power gate solidly on; and a turn off finisher circuit is responsive to the disable signal transitioning to off and to the test signal for holding said power gate solidly off.
摘要翻译： 电力从全球地形门控到电压岛，同时控制漏电和管理瞬时电源噪声。 电压岛包括场效应晶体管（FET）功率门，到全局电压源的第一连接和到禁用信号源的第二连接，以及用于向岛上的器件供电的岛电压网。 电源门控制电路响应于禁用信号源，用于产生用于在禁用信号源变为逻辑“1”时选择性地关断FET功率门的测试信号，并且用于作为所述禁用源导通FET功率门 转到逻辑“0”。 FET功率门响应于禁用信号源关闭，以将岛电压网连接到全局电压源。 打开整理器电路响应于禁用信号转换到接通和用于保持电源门的测试信号; 并且关闭整理器电路响应于禁用信号转换到关闭和用于保持所述电源门的测试信号。
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公开(公告)号：US06883152B2
公开(公告)日：2005-04-19
申请号：US10867914
申请日：2004-06-15
CPC分类号： G06F17/5045
摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要翻译： 用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。 本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。
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公开(公告)号：US06545521B2
公开(公告)日：2003-04-08
申请号：US09895778
申请日：2001-06-29
IPC分类号： H03L500
CPC分类号： H04L25/0292 , H03K19/00315 , H04L25/0266 , H04L25/0272
摘要： The present invention provides a receiver device having multiple voltage supplies that allows the output stage of the receiver device to go to a safe state whenever its voltage is disconnected or powered-down, independent of any of its normal control circuits. Furthermore, the isolation of the multiple voltage supplies provides a low skew at the output of the receiver device.
摘要翻译： 本发明提供了一种具有多个电压源的接收机设备，每当其电压断开或掉电时，接收机设备的输出级都能够进入安全状态，独立于其任何正常的控制电路。 此外，多个电压源的隔离在接收器件的输出处提供低偏移。
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公开(公告)号：US06362653B1
公开(公告)日：2002-03-26
申请号：US09777286
申请日：2001-02-06
IPC分类号： H03K1716
CPC分类号： H03K19/00315
摘要： A high voltage tolerant receiver that matches a voltage drop across an NFET pass-gate at the input to the receiver with a voltage drop across a semiconductor device, formatted as a diode, and connected between an input stage and an input stage voltage supply source.
摘要翻译： 一个高耐压接收器，其匹配在接收器的输入端上的NFET通过栅极上的电压降，并且跨接半导体器件的压降，被格式化为二极管，并连接在输入级和输入级电压源之间。
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公开(公告)号：US6140846A
公开(公告)日：2000-10-31
申请号：US183707
申请日：1998-10-30
申请人： Francis Chan , Steven P. Koch , Douglas W. Stout
发明人： Francis Chan , Steven P. Koch , Douglas W. Stout
IPC分类号： H03K19/003 , H03B1/00 , H03K3/00
CPC分类号： H03K19/00315
摘要： A driver circuit has an input terminal at which a first signal having a first voltage swing is applied, and an output terminal at which: (i) a second signal having a second voltage swing is provided to external circuitry, and (ii) a third signal having a third voltage swing is received from the external circuitry. A level shifter circuit is coupled to the input terminal and translates the first signal to the second signal. The level shifter circuit includes circuitry which regulates the switching rate of the driver circuit. An output circuit is coupled between the level shifter circuit and the output terminal which drives the external circuitry with the second signal received from the level shifter circuit. The output circuit has a floating well, and a bias circuit is coupled between the output terminal and the well of the output circuit. The bias circuit biases the well proportional to the third voltage swing when the third signal is received at the output terminal. A feedback circuit is coupled between the output terminal and the output circuit. The feedback circuit deactivates at least a portion of the output circuit responsive to the third signal being received at the output terminal.
摘要翻译： 驱动器电路具有施加具有第一电压摆幅的第一信号的输入端子和输出端子，其中：（i）具有第二电压摆幅的第二信号被提供给外部电路，以及（ii）第三 从外部电路接收具有第三电压摆幅的信号。 电平移位器电路耦合到输入端并将第一信号转换为第二信号。 电平移位器电路包括调节驱动器电路的开关速率的电路。 输出电路耦合在电平移位器电路和输出端之间，该电平移位器电路与从电平移位器电路接收到的第二信号驱动外部电路。 输出电路具有浮动阱，并且偏置电路耦合在输出端和输出电路的阱之间。 当在输出端接收到第三信号时，偏置电路偏压阱与第三电压摆幅成比例。 反馈电路耦合在输出端和输出电路之间。 响应于在输出端接收到的第三信号，反馈电路去激活输出电路的至少一部分。
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