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    Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors
    1.
    发明授权
    Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors 有权
    半导体结构和半导体结构设计方法，以避免在低压部分高压启动闭锁

    公开(公告)号：US08423936B2

    公开(公告)日：2013-04-16

    申请号：US13358105

    申请日：2012-01-25

    Applicant: Steven H. Voldman

    Inventor： Steven H. Voldman

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  H01L23/585 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method and semiconductor structure to avoid latch-up is disclosed. The method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit.

    Abstract translation: 公开了一种避免闩锁的方法和半导体结构。 该方法包括识别半导体芯片上的至少一个高电压器件，识别半导体芯片上的由保护环与所识别的至少一个高电压器件分离的电路，评估该电路的闩锁状态，以及当 发生闩锁状态，调整电路中的接触电路间距。

    Structure and method for latchup improvement using through wafer via latchup guard ring
    2.
    发明授权
    Structure and method for latchup improvement using through wafer via latchup guard ring 有权
    用于通过闭锁保护环通过晶片的闩锁改进的结构和方法

    公开(公告)号：US08390074B2

    公开(公告)日：2013-03-05

    申请号：US13150437

    申请日：2011-06-01

    Applicant: Steven H. Voldman

    Inventor： Steven H. Voldman

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

    CPC classification number: H01L27/0921

    Abstract: A structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.

    Abstract translation: 用于防止闩锁的结构。 该结构包括闭锁敏感结构和限制闩锁敏感结构的穿透晶片通孔结构，以防止寄生载流子注入到闩锁敏感结构中。

    Wrapped gate junction field effect transistor
    3.
    发明授权
    Wrapped gate junction field effect transistor 有权
    封装栅结场效应晶体管

    公开(公告)号：US07977714B2

    公开(公告)日：2011-07-12

    申请号：US11875190

    申请日：2007-10-19

    Applicant: John Ellis-Monaghan ,  Richard A. Phelps ,  Robert M. Rassel ,  Steven H. Voldman ,  Michael J. Zierak

    Inventor： John Ellis-Monaghan ,  Richard A. Phelps ,  Robert M. Rassel ,  Steven H. Voldman ,  Michael J. Zierak

    IPC: H01L29/808 ,  H01L21/337

    CPC classification number: H01L29/808 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/66924

    Abstract: A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.

    Abstract translation: 提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。 所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。 此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。 包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过 所述至少一个半导体通道。 通过采用多个通道，JFET可以提供高导通电流。

    High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature
    4.
    发明授权
    High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature 有权
    高容差TCR平衡型高电流电阻，用于射频CMOS和射频SiGe BiCMOS应用以及基于分级的分级参数化电池设计套件，具有可调TCR和ESD电阻镇流功能

    公开(公告)号：US07949983B2

    公开(公告)日：2011-05-24

    申请号：US12234473

    申请日：2008-09-19

    Applicant: Ebenezer E. Eshun ,  Steven H. Voldman

    Inventor： Ebenezer E. Eshun ,  Steven H. Voldman

    IPC: G06F17/50

    CPC classification number: H01C7/06 ,  H01L27/0288 ,  H01L27/0802 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.

    Abstract translation: 因此，电阻器件结构及其制造方法，其中电阻器件结构发明包括多个交替导电膜和绝缘膜层，至少两个导电膜层并联电连接以提供通过电阻器的高电流 器件在高频下具有升高的温度和机械稳定性。 交替导电膜和绝缘膜层可以是平面或非平面的几何空间取向。 交替导电膜和绝缘膜层可以包括横向和垂直部分，其被设计成能够通过物理电阻器内的自镇流效应在结构本身内实现均匀的电流密度流动。 提供了具有图形和原理图功能的计算机辅助设计工具，以便能够为电阻元件生成分层参数化单元，具有提供TCR，TCR匹配以及高电流和ESD鲁棒性的定制，个性化和可调性的能力。

    Electrostatic Discharge Structures and Methods of Manufacture
    5.
    发明申请
    Electrostatic Discharge Structures and Methods of Manufacture 有权
    静电放电结构及制造方法

    公开(公告)号：US20100321842A1

    公开(公告)日：2010-12-23

    申请号：US12489774

    申请日：2009-06-23

    Applicant: Ephrem G. GEBRESELASIE ,  Steven H. VOLDMAN

    Inventor： Ephrem G. GEBRESELASIE ,  Steven H. VOLDMAN

    IPC: H02H9/00 ,  H01L21/3205

    CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.

    Abstract translation: 提供了具有与通过晶片通孔结构和制造方法的连接的静电放电（ESD）结构。 该结构包括与通过晶片通孔串联电连接的静电放电（ESD）网络。 更具体地，ESD电路包括位于接合焊盘下方的接合焊盘和ESD网络。 ESD电路还包括直接与ESD网络串联电连接并且还电连接到VSS的直通晶片通孔结构。

    Dendrite growth control circuit
    7.
    发明授权
    Dendrite growth control circuit 失效
    树枝生长控制电路

    公开(公告)号：US07807562B2

    公开(公告)日：2010-10-05

    申请号：US12256221

    申请日：2008-10-22

    Applicant: Douglas B. Hershberger ,  Steven H. Voldman ,  Michael J. Zierak

    Inventor： Douglas B. Hershberger ,  Steven H. Voldman ,  Michael J. Zierak

    IPC: H01L21/4763

    CPC classification number: H01L21/76838

    Abstract: A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.

    Abstract translation: 提供了一种电路，其防止由于树突形成电流而在半导体器件处理期间互连上的枝晶形成。 电路包括位于至少一个枝晶形成电流路径中的开关。 该开关被配置为在处理期间处于打开状态或处于“关闭”状态，并且在处理之后被配置为闭合或处于“接通”状态以允许半导体器件正常工作。 开关可以包括nFET或pFET，这取决于其用于控制​​或防止枝晶形成的环境。 当在制造的半导体器件的操作期间提供输入信号时，开关可以被配置为改变为“闭合”状态。

    Semiconductor devices
    8.
    发明授权
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US07755161B2

    公开(公告)日：2010-07-13

    申请号：US12237148

    申请日：2008-09-24

    Applicant: Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

    Inventor： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

    IPC: H01L29/00

    CPC classification number: H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

    Abstract: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

    Abstract translation: 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

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