公开(公告)号：US6041170A

公开(公告)日：2000-03-21

申请号：US904233

申请日：1997-07-31

申请人： Peter Feldmann ,  Roland W. Freund

发明人： Peter Feldmann ,  Roland W. Freund

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and apparatus for generating and analyzing a reduced-order model of a linear circuit. The method and apparatus generates the symmetric multi-port transfer function of an RLC circuit. The invention employs a novel symmetric block-Lanczos-type procedure, termed SyMPVL for Symmetric Matrix Pade via Lanczos, to reduce original circuit matrices to a pair of banded symmetric matrices. When the circuit comprises only two of the three RLC components, the matrices are also positive definite. These matrices are typically much smaller than the original circuit matrices and determine a reduced-order model of the original multi-port transfer function of the circuit. The reduced transfer function represents a matrix-Pade approximation of the original multi-port matrix transfer function.

摘要翻译： 一种用于生成和分析线性电路的低阶模型的方法和装置。 该方法和装置产生RLC电路的对称多端口传送功能。 本发明采用新型的对称块-Lanczos型方法，称为对称矩阵Pad + E的SyMPVL，通过Lanczos的acu e + EE，以将原始电路矩阵减少到一对带状对称矩阵。 当电路仅包括三个RLC组件中的两个时，矩阵也是正定的。 这些矩阵通常远小于原始电路矩阵，并且确定电路的原始多端口传递函数的降阶模型。 减少的传递函数表示原始多端口矩阵传递函数的矩阵Pad + E，acu e + EE近似。

公开(公告)号：US5537329A

公开(公告)日：1996-07-16

申请号：US269230

申请日：1994-06-30

申请人： Peter Feldmann ,  Roland W. Freund

发明人： Peter Feldmann ,  Roland W. Freund

IPC分类号： G01R27/28 ,  G06F17/50 ,  G06G7/19

CPC分类号： G06F17/5036

摘要： A circuit analyzer and method are disclosed for generating and outputting a Pade via Lanczos (PVL) approximation of a frequency response of a circuit from input circuit parameters. A processing unit having a processor, memory, and stored programs processes the input circuit parameters, determines a block tridiagonal matrix by an iterative look-ahead Lanczos procedure, and calculates a Pade approximant from the block tridiagonal matrix, including poles, zeros, and residues. The look-ahead Lanczos procedure employs non-singular matrices to ensure numerical stability of the iterative calculation of the components of the block tridiagonal matrix. The output is an approximation of a plurality of frequencies at which any poles and zeros of the impulse response of the circuit occur. A graphical representation of the approximated frequency response is also produced, and qualitative measurements of the accuracy of the approximated poles are provided.

摘要翻译： 公开了一种电路分析器和方法，用于通过来自输入电路参数的电路的频率响应的Lanczos（PVL）近似生成和输出Padé。 具有处理器，存储器和存储的程序的处理单元处理输入电路参数，通过迭代前瞻Lanczos程序确定块三对角矩阵，并从块三对角矩阵中计算包括极点，零点和残差的Padé近似值 。 先行Lanczos程序使用非奇异矩阵来确保块三对角矩阵的分量的迭代计算的数值稳定性。 输出是电路的脉冲响应的任何极点和零点的多个频率的近似值。 还产生近似频率响应的图形表示，并且提供近似极点的精度的定性测量。

公开(公告)号：US08290760B2

公开(公告)日：2012-10-16

申请号：US12163318

申请日：2008-06-27

申请人： Emrah Acar ,  Bhavna Agrawal ,  Peter Feldmann ,  Ying Liu ,  Steven G. Walker

发明人： Emrah Acar ,  Bhavna Agrawal ,  Peter Feldmann ,  Ying Liu ,  Steven G. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.

摘要翻译： 提供了使用初始电荷信息分析电路的解决方案。 特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。 电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。 然后基于初始电荷在一组输入周期上模拟电路的操作。 在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。 该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。 此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

公开(公告)号：US20120245904A1

公开(公告)日：2012-09-27

申请号：US13071029

申请日：2011-03-24

申请人： SOROUSH ABBASPOUR ,  Peter Feldmann ,  Safar Hatami

发明人： SOROUSH ABBASPOUR ,  Peter Feldmann ,  Safar Hatami

IPC分类号： G06F17/10

CPC分类号： G06F17/5036 ,  G06F2217/84

摘要： In one embodiment, the invention is a method and apparatus for waveform-based digital gate modeling for timing analysis. One embodiment of a method for modeling a gate of an integrated circuit chip includes building a transform matrix that indexes each input waveform/output waveform pair in a gate library to a plurality of different capacitive loads, obtaining an input waveform and a capacitive load associated with the gate, and, mapping the input waveform and the capacitive load to an output waveform for the gate, in accordance with the transform matrix.

摘要翻译： 在一个实施例中，本发明是用于时序分析的基于波形的数字门模拟的方法和装置。 用于对集成电路芯片的栅极进行建模的方法的一个实施例包括建立变换矩阵，其将栅极库中的每个输入波形/输出波形对索引到多个不同的容性负载，获得输入波形和与 栅极，并且根据变换矩阵将输入波形和电容性负载映射到门的输出波形。

公开(公告)号：US08108815B2

公开(公告)日：2012-01-31

申请号：US12471653

申请日：2009-05-26

申请人： Soroush Abbaspour ,  Peter Feldmann

发明人： Soroush Abbaspour ,  Peter Feldmann

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified.

摘要翻译： 一种方法和系统，通过在给定分布的过程和环境变化源的情况下，通过执行统计时序分析检测到的定时违规来提高集成电路（IC）芯片的性能。 使用最小失真标准将分布量化为离散值。 对于IC电路的每个定时节点，使用离散值的组合的子集对定时参数执行离散的最小和最大操作。 然后离散的最小和最大运算的结果被去量化并传播到随后的定时节点及其边缘。 该过程继续，直到达到IC芯片的一个或多个主要输入和输出。 通过消除所有定时违规来修改IC芯片的设计。

公开(公告)号：US20110276933A1

公开(公告)日：2011-11-10

申请号：US12774766

申请日：2010-05-06

申请人： Revanta Banerji ,  Soroush Abbaspour ,  Peter Feldmann ,  Hemlata Gupta

发明人： Revanta Banerji ,  Soroush Abbaspour ,  Peter Feldmann ,  Hemlata Gupta

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/08 ,  G06F2217/78 ,  G06F2217/82 ,  G06F2217/84

摘要： A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.

摘要翻译： 一种用于通过预处理可用库的表征点来准确地执行定时，功率和噪声分析的方法，存储分析的时间消耗部分并且在主动运行期间利用预处理信息来计算期望PVT处的属性 点。 PVT空间优选地分为三角形或矩形区域，优选地使用Delaunay三角测量法获得。 在一个实施例中，本发明对特征库执行前期预处理步骤，以计算独立于特定实例的内插函数的静态部分; 以及允许特定实例的插值的系数矩阵。

公开(公告)号：US20110245774A1

公开(公告)日：2011-10-06

申请号：US13164072

申请日：2011-06-20

申请人： Ulrich Haueter ,  Sandro Niederhauser ,  Peter Feldmann ,  Christian Hof

发明人： Ulrich Haueter ,  Sandro Niederhauser ,  Peter Feldmann ,  Christian Hof

IPC分类号： A61B17/34

CPC分类号： A61B5/6848 ,  A61B5/0002 ,  A61B5/14503 ,  A61B5/14532 ,  A61B5/6849 ,  A61B17/3403 ,  A61B17/3415 ,  A61B2017/3492 ,  A61M5/158 ,  A61M2005/1581 ,  A61M2005/1585 ,  A61M2005/1587 ,  A61M2039/0202 ,  A61M2039/0205

摘要： A device for facilitating the use or application of skin penetrators, the device including a puncturing part for piercing the skin, an indwelling part which can be introduced into the skin through an opening generated by the puncturing part and remains there, wherein the puncturing part and indwelling part are operably associated with the device, and a guide operably associated with the device, wherein, in use, the indwelling part is moved, via the guide, into a position of use after the puncturing part has pierced the skin. In some embodiments, the puncturing and indwelling parts are separate from each other prior to use. A method of using skin penetrators is encompassed and includes sequentially introducing the puncturing part and the indwelling part into the skin.

摘要翻译： 一种用于促进皮肤穿透器的使用或应用的装置，所述装置包括用于刺穿皮肤的穿刺部分，可以通过穿刺部产生的开口引入皮肤并留在皮肤上的留置部分，其中穿刺部分和 与所述装置可操作地相关联的引导部分和与所述装置可操作地相关联的引导件，其中在使用中，所述留置部分经由所述引导件在所述穿刺部件刺穿所述皮肤之后移动到使用位置。 在一些实施例中，穿刺和留置部分在使用之前彼此分离。 包括使用皮肤穿透器的方法，并且包括将穿刺部分和留置部分顺序地引入皮肤。

公开(公告)号：US07941775B2

公开(公告)日：2011-05-10

申请号：US12044223

申请日：2008-03-07

申请人： Soroush Abbaspour ,  Peter Feldmann

发明人： Soroush Abbaspour ,  Peter Feldmann

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured to perform a timing analysis on the at least one logic gate and a noise analysis component is configured to perform a noise analysis. A waveform propagation model synthesizer component is configured to dynamically synthesize a waveform propagation model as a function of the timing analysis. The waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.

摘要翻译： 描述了使用定时分析结果通过逻辑门执行任意波形传播的方法。 在一个实施例中，存在用于确定噪声对具有至少一个逻辑门的数字集成电路的影响的任意波形传播工具。 定时分析部件被配置为对所述至少一个逻辑门执行定时分析，并且噪声分析部件被配置为执行噪声分析。 波形传播模型合成器组件被配置为动态地合成作为时序分析的函数的波形传播模型。 波形传播模型合成器部件还被配置为施加包括噪声波形或噪声毛刺波形中的一个的任意电压波形，并且从动态合成的波形传播模型确定任意电压波形对至少一个逻辑门的影响。

公开(公告)号：US20100306723A1

公开(公告)日：2010-12-02

申请号：US12471653

申请日：2009-05-26

申请人： Soroush Abbaspour ,  Peter Feldmann

发明人： Soroush Abbaspour ,  Peter Feldmann

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified.

摘要翻译： 一种方法和系统，通过在给定分布的过程和环境变化源的情况下，通过执行统计时序分析检测到的定时违规来提高集成电路（IC）芯片的性能。 使用最小失真标准将分布量化为离散值。 对于IC电路的每个定时节点，使用离散值的组合的子集对定时参数执行离散的最小和最大操作。 然后离散的最小和最大运算的结果被去量化并传播到随后的定时节点及其边缘。 该过程继续，直到达到IC芯片的一个或多个主要输入和输出。 通过消除所有定时违规来修改IC芯片的设计。

公开(公告)号：US20080306716A1

公开(公告)日：2008-12-11

申请号：US12192481

申请日：2008-08-15

申请人： Peter Feldmann ,  Jason D. Morsey ,  Barry J. Rubin

发明人： Peter Feldmann ,  Jason D. Morsey ,  Barry J. Rubin

IPC分类号： G06F7/60 ,  G06F1/00 ,  G06G7/48

CPC分类号： G06F17/12

摘要： This invention relates to computing numerical solutions of linear systems of equations, specifically to implementing preconditioning of the coefficient matrix of such a system. The preconditioning applies to any coefficient matrix, dense or sparse, based on the solutions of a physical problem of unknown functions, commonly referred to as basis or interpolation functions, where the basis function spans more then one mesh element. Examples of such linear systems can result from, as examples, an electromagnetic analysis of printed circuit boards or field scattering in radar applications, fluid mechanics and acoustics. A method and system to compute a preconditioner for a coefficient matrix A that is compatible with the linear system of equations that provides basis function support over at least two mesh elements. Coupling of the preconditioner between partitions of a portioned mesh representation is only through basis functions at the partition boundaries.

摘要翻译： 本发明涉及计算线性方程组的数值解，具体涉及实现这种系统的系数矩阵的预处理。 基于未知函数的物理问题的解决方案，通常称为基础函数或插值函数，其中基函数跨越多于一个网格元素，该预处理适用于任何密集或稀疏的系数矩阵。 作为示例，这种线性系统的示例可以从印刷电路板的电磁分析或雷达应用中的场散射，流体力学和声学等方面得到。 一种用于计算系数矩阵A的预处理器的方法和系统，该系数矩阵A与在至少两个网格元素上提供基函数支持的线性方程组兼容。 分段网格表示的分区之间的预处理器的耦合仅通过分区边界处的基函数。