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公开(公告)号：US20060123373A1
公开(公告)日：2006-06-08
申请号：US11007039
申请日：2004-12-08
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
CPC分类号： G06F17/5072
摘要： A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.
摘要翻译： 用于在集成电路布局图案中布局模块的系统具有单元库和单元布置系统。 细胞库包括多个细胞。 单元布置系统适于从单元库中选择一个或多个单元，并将每个选定单元局部放置在模块布局内，使得所选单元格的每个单元管脚和模块布局的每个端口都占用一个唯一的垂直布线轨道 模块布局。
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公开(公告)号：US20080270505A1
公开(公告)日：2008-10-30
申请号：US11741865
申请日：2007-04-30
IPC分类号： G06F7/00
CPC分类号： G06F7/724 , H04L9/0631 , H04L2209/122 , H04L2209/125
摘要： A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T (n+1) basing on known T n. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).
摘要翻译： 可以快速计算T
mm“file =”US20080270505A1-20081030-P00001.TIF“img-content =”character“img-format =”tif“/> n。 调度（调用乘法单元的频率）可以被认为是算法的参数。 所提出的“差分”单元的架构在速度（延迟）和面积（门数）方面都是有效的。
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公开(公告)号：US20080049719A1
公开(公告)日：2008-02-28
申请号：US11924385
申请日：2007-10-25
IPC分类号： H04L13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译： 路由复用器系统基于所选择的p个输入的排列来提供p个输出。 多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入端的位的值，以直接或转置的顺序向两个输出提供两个输入端的信号。 模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。 多个控制位表各自包含基于相应置换的布置中的多个位。 存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。
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公开(公告)号：US20070276648A1
公开(公告)日：2007-11-29
申请号：US11706943
申请日：2007-02-13
申请人： Alexander Andreev , Anatoli Bolotov
发明人： Alexander Andreev , Anatoli Bolotov
IPC分类号： G06F9/455
CPC分类号： G01R31/31917 , Y10S707/99933
摘要： The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.
摘要翻译： 本发明涉及一种用于最长前缀搜索引擎的顺序测试器。 测试器可以包括最长的前缀搜索引擎，用于向最长的前缀搜索引擎提供几乎随机的输入命令的输入生成器，并输出可以表示最长前缀搜索引擎的搜索表的浮动矩形，编码模块 用于向最长前缀搜索引擎提供地址和前缀信息，用于向最长前缀搜索引擎提供数据信息的映射模块，用于执行超级搜索操作的超级搜索引擎和用于计算最长前缀搜索引擎的预测输出的分析器 并将预测输出与由最长前缀搜索引擎计算的实际输出进行比较。
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公开(公告)号：US20060085777A1
公开(公告)日：2006-04-20
申请号：US10936202
申请日：2004-09-08
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/02 , G11C5/04
摘要： The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access. Then, positions for the data pins of the top module (and at least one control pin, if applicable) of the top module are assigned in the top module. The instances are arranged within the top module. Signal routing for the instances and the top module are implemented. Power routing is performed for the instances and the top module.
摘要翻译： 本发明提供一种包括诸如RRAM存储矩阵等存储矩阵中的基本模块的实例的顶部模块的布局方法。 顶部模块和基本模块可以各自包括数据引脚和至少一个控制引脚，或者顶部模块和基本模块可以各自包括数据引脚，并且可以不包括任何控制引脚。 基本模块的实例的数据引脚在顶部模块中复制。 当至少一个控制引脚被包括在顶部模块和基本模块中时，控制信号可以通过将实例的对应的控制引脚和相应的控制引脚相连接在一起，在基本模块和顶部模块的实例之间共享 顶部模块。 本方法可以包括以下步骤。 在图书馆准备阶段，顶部模块中的标准单元的数据引脚（和控制引脚（如果适用））垂直延伸以方便访问。 然后，顶部模块的顶部模块（和至少一个控制引脚（如果适用））的数据引脚的位置被分配在顶部模块中。 实例被布置在顶部模块内。 实现实例和顶层模块的信号路由。 为实例和顶部模块执行电源路由。
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公开(公告)号：US20050240746A1
公开(公告)日：2005-10-27
申请号：US10830739
申请日：2004-04-25
CPC分类号： G06F12/02 , G06F17/5045
摘要： A plurality of user-defined memories are mapped to pre-defined basic memories, such as defined on a base platform. The user-defined memories are dividing into classes of similar memories. A mapping technique is selected for members of a selected class of user-defined memories that minimizes the ratio (maxi,j(USEDi,j/AVAILi,j)) of basic memories that have been mapped to basic memories that are available for mapping. If the number of different memory mappings is smaller than a threshold the mapping technique is applied to each user-defined memory. If the number of different memory mappings is greater than the threshold, the groups are arranged in ordered queues of single memory types based on a mapping price and the mapping technique is selected based on a memory of each group and is applied to each user-defined memory in the respective group.
摘要翻译： 多个用户定义的存储器映射到预定义的基本存储器，诸如在基础平台上定义的。 用户定义的存储器被分成类似的存储器的类别。 为选定类别的用户定义的存储器的成员选择映射技术，其使比率最小化（最大值，最小化，最小化，最小化 ，j））已被映射到可用于映射的基本存储器的基本存储器。 如果不同的存储器映射的数量小于阈值，则映射技术被应用于每个用户定义的存储器。 如果不同内存映射的数量大于阈值，则基于映射价格将组排列成单个存储器类型的有序队列，并且基于每个组的存储器选择映射技术并将其应用于每个用户定义 记忆在相应的组。
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47.发明申请FIFO memory with single port memory modules for allowing simultaneous read and write operations 有权具有单端口存储器模块的FIFO存储器，用于允许同时的读写操作公开(公告)号：US20050091465A1
公开(公告)日：2005-04-28
申请号：US10692664
申请日：2003-10-23
摘要： The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.
摘要翻译： 本发明涉及具有单端口存储器模块的FIFO存储器，其可以允许同时的读和写操作。 在本发明的示例性方面，一种采用具有半容量的单端口存储器模块的FIFO存储器来执行同时读和写操作的方法包括以下步骤：（a）提供用于偶数地址的第一单端口存储器模块 的读或写操作; （b）提供用于读或写操作的奇数地址的第二单端口存储器模块; （c）交替地址和奇地址; 和（d）当读请求和写请求都在时钟周期到达第一单端口存储器模块或第二单端口存储器模块时，在当前时钟周期满足读请求并在下一个时刻满足写请求 时钟周期。
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48.发明授权Method and apparatus for minimization of net delay by optimal buffer insertion 有权通过最佳缓冲区插入最小化净延迟的方法和装置公开(公告)号：US06519746B1
公开(公告)日：2003-02-11
申请号：US09685990
申请日：2000-10-10
IPC分类号： G06F945
CPC分类号： G06F17/505
摘要： The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.
摘要翻译： 本发明涉及一种减少网络延迟的方法。 该方法包括构建时空网格，所述时间网格对应于网络，将波通过时空网格，所述波具有波值，并在所述时空网格上的点处插入缓冲器 其中缓冲器的插入增加波值。 缓冲区可以是负缓冲区或正缓冲区。 通常，第二波与第一波同时通过时空网格。 通常，第二波和第一波反转。
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