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公开(公告)号：US20060085777A1
公开(公告)日：2006-04-20
申请号：US10936202
申请日：2004-09-08
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/02 , G11C5/04
摘要： The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access. Then, positions for the data pins of the top module (and at least one control pin, if applicable) of the top module are assigned in the top module. The instances are arranged within the top module. Signal routing for the instances and the top module are implemented. Power routing is performed for the instances and the top module.
摘要翻译： 本发明提供一种包括诸如RRAM存储矩阵等存储矩阵中的基本模块的实例的顶部模块的布局方法。 顶部模块和基本模块可以各自包括数据引脚和至少一个控制引脚，或者顶部模块和基本模块可以各自包括数据引脚，并且可以不包括任何控制引脚。 基本模块的实例的数据引脚在顶部模块中复制。 当至少一个控制引脚被包括在顶部模块和基本模块中时，控制信号可以通过将实例的对应的控制引脚和相应的控制引脚相连接在一起，在基本模块和顶部模块的实例之间共享 顶部模块。 本方法可以包括以下步骤。 在图书馆准备阶段，顶部模块中的标准单元的数据引脚（和控制引脚（如果适用））垂直延伸以方便访问。 然后，顶部模块的顶部模块（和至少一个控制引脚（如果适用））的数据引脚的位置被分配在顶部模块中。 实例被布置在顶部模块内。 实现实例和顶层模块的信号路由。 为实例和顶部模块执行电源路由。
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公开(公告)号：US07818703B2
公开(公告)日：2010-10-19
申请号：US11757200
申请日：2007-06-01
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.
摘要翻译： 用于在集成电路布局图案中布局模块的系统具有单元库和单元布置系统。 细胞库包括多个细胞。 单元布置系统适于从单元库中选择一个或多个单元，并将每个选定单元局部放置在模块布局内，使得所选单元格的每个单元管脚和模块布局的每个端口都占用一个唯一的垂直布线轨道 模块布局。
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公开(公告)号：US20080016482A1
公开(公告)日：2008-01-17
申请号：US11757200
申请日：2007-06-01
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.
摘要翻译： 用于在集成电路布局图案中布局模块的系统具有单元库和单元布置系统。 细胞库包括多个细胞。 单元布置系统适于从单元库中选择一个或多个单元，并将每个选定单元局部放置在模块布局内，使得所选单元格的每个单元管脚和模块布局的每个端口都占用一个唯一的垂直布线轨道 模块布局。
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公开(公告)号：US07246337B2
公开(公告)日：2007-07-17
申请号：US11007039
申请日：2004-12-08
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.
摘要翻译： 用于在集成电路布局图案中布局模块的系统具有单元库和单元布置系统。 细胞库包括多个细胞。 单元布置系统适于从单元库中选择一个或多个单元，并将每个选定单元局部放置在模块布局内，使得所选单元格的每个单元管脚和模块布局的每个端口都占用一个唯一的垂直布线轨道 模块布局。
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公开(公告)号：US20060123373A1
公开(公告)日：2006-06-08
申请号：US11007039
申请日：2004-12-08
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
CPC分类号： G06F17/5072
摘要： A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.
摘要翻译： 用于在集成电路布局图案中布局模块的系统具有单元库和单元布置系统。 细胞库包括多个细胞。 单元布置系统适于从单元库中选择一个或多个单元，并将每个选定单元局部放置在模块布局内，使得所选单元格的每个单元管脚和模块布局的每个端口都占用一个唯一的垂直布线轨道 模块布局。
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公开(公告)号：US07194717B2
公开(公告)日：2007-03-20
申请号：US10936202
申请日：2004-09-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/02 , G11C5/04
摘要： The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access. Then, positions for the data pins of the top module (and at least one control pin, if applicable) of the top module are assigned in the top module. The instances are arranged within the top module. Signal routing for the instances and the top module are implemented. Power routing is performed for the instances and the top module.
摘要翻译： 本发明提供一种包括诸如RRAM存储矩阵等存储矩阵中的基本模块的实例的顶部模块的布局方法。 顶部模块和基本模块可以各自包括数据引脚和至少一个控制引脚，或者顶部模块和基本模块可以各自包括数据引脚，并且可以不包括任何控制引脚。 基本模块的实例的数据引脚在顶部模块中复制。 当至少一个控制引脚被包括在顶部模块和基本模块中时，控制信号可以通过将实例的对应的控制引脚和相应的控制引脚相连接在一起，在基本模块和顶部模块的实例之间共享 顶部模块。 本方法可以包括以下步骤。 在图书馆准备阶段，顶部模块中的标准单元的数据引脚（和控制引脚（如果适用））垂直延伸以方便访问。 然后，顶部模块的顶部模块（和至少一个控制引脚（如果适用））的数据引脚的位置被分配在顶部模块中。 实例被布置在顶部模块内。 实现实例和顶层模块的信号路由。 为实例和顶部模块执行电源路由。
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公开(公告)号：US07546505B2
公开(公告)日：2009-06-09
申请号：US11557513
申请日：2006-11-08
申请人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
发明人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
CPC分类号： G11C29/16 , G11C29/34 , G11C2029/0401 , G11C2029/1204 , G11C2029/2602
摘要： A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.
摘要翻译： 内存自检电路在内存矩阵中。 矩阵内的存储单元被排列成列。 该电路只有一个内存测试控制器，适用于启动命令并接收结果。 传输控制器与存储单元的列配对。 控制器从存储器测试控制器接收命令，测试列内的测试存储单元，接收测试结果，并将结果提供给存储器测试控制器。 运输控制器以三种模式运行。 生产测试模式测试不同列中的存储单元，使用与列相关联的控制器累积给定列的结果。 生产测试模式从控制器检索结果。 诊断测试模式测试一列内的存储单元，同时检索列的结果。
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公开(公告)号：US07667494B2
公开(公告)日：2010-02-23
申请号：US12058881
申请日：2008-03-31
IPC分类号： G11C19/00 , H03K19/173
CPC分类号： G11C19/00 , G06F9/3869 , Y10T29/49002
摘要： Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.
摘要翻译： 为快速不平衡管道架构提供了方法和装置。 公开的流水线缓冲器包括串联连接的多个存储器寄存器，多个存储器寄存器中的每一个，诸如触发器，具有使能输入和时钟输入; 以及控制存储器寄存器，其具有驱动多个存储器寄存器的使能输入的输出，由此控制存储器寄存器的输入上的预定二进制值在下一个时钟周期上移位多个存储器寄存器的值。 多个公开的管道自助餐可以被配置为多级配置。 多个存储寄存器中的至少一个可以包括同步流水线缓冲器的锁存储寄存器。 流水线缓冲器可以可选地包括延迟门以延迟时钟信号和反相器以反转延迟的时钟信号。 时钟信号可以由延迟门延迟，使得流水线缓冲器的输出在正确的时间被施加到流水线缓冲器的下一级。
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公开(公告)号：US20090243657A1
公开(公告)日：2009-10-01
申请号：US12058881
申请日：2008-03-31
IPC分类号： H03K19/096 , H01S4/00 , H03L7/00
CPC分类号： G11C19/00 , G06F9/3869 , Y10T29/49002
摘要： Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.
摘要翻译： 为快速不平衡管道架构提供了方法和装置。 公开的流水线缓冲器包括串联连接的多个存储器寄存器，多个存储器寄存器中的每一个，诸如触发器，具有使能输入和时钟输入; 以及控制存储器寄存器，其具有驱动多个存储器寄存器的使能输入的输出，由此控制存储器寄存器的输入上的预定二进制值在下一个时钟周期上移位多个存储器寄存器的值。 多个公开的管道自助餐可以被配置为多级配置。 多个存储寄存器中的至少一个可以包括同步流水线缓冲器的锁存储寄存器。 流水线缓冲器可以可选地包括延迟门以延迟时钟信号和反相器以反转延迟的时钟信号。 时钟信号可以由延迟门延迟，使得流水线缓冲器的输出在正确的时间被施加到流水线缓冲器的下一级。
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公开(公告)号：US07028274B1
公开(公告)日：2006-04-11
申请号：US11054460
申请日：2005-02-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for transforming a customer's memory design into an RRAM memory design. A port mapping table is created that lists the ports of the customer memories, and an instance types table is created that lists the customer memories. For each customer memory that is listed in the instance types table, any virtual buffer nets are removed, and any virtual buffers are removed. Any loose nets so created are reconnected to an RRAM cell in the RRAM memory design. The customer memory instance are then removed. A constraints file is updated from customer memory port designations to RRAM port designations. Automated test logic is inserted into the RRAM memory design, layout on the RRAM memory design is performed, and timing constraints on the RRAM memory design are satisfied. A modified version of the RRAM memory design is returned to the customer for verification. The modified version is made using the port mapping table. Each RRAM matrix is replaced with the customer memories it replaced, the removed virtual buffer nets and virtual buffers are left out, and other parts of the RRAM memory design are left unchanged.
摘要翻译： 将客户的存储器设计转换为RRAM存储器设计的方法。 创建一个端口映射表，其中列出了客户端口的存储器，并创建了一个列出客户内存的实例类型表。 对于实例类型表中列出的每个客户内存，将删除任何虚拟缓冲区网络，并删除任何虚拟缓冲区。 任何如此创建的松散网络都将重新连接到RRAM内存设计中的RRAM单元。 然后删除客户内存实例。 约束文件从客户内存端口名称更新为RRAM端口名称。 将自动测试逻辑插入到RRAM存储器设计中，执行RRAM存储器设计的布局，并满足RRAM存储器设计的时序约束。 将修改版本的RRAM存储器设计返回给客户进行验证。 修改版本使用端口映射表进行。 每个RRAM矩阵被替换的客户存储器替代，删除的虚拟缓冲器网络和虚拟缓冲器被省略，并且RRAM存储器设计的其他部分保持不变。
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