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公开(公告)号：US20250111463A1
公开(公告)日：2025-04-03
申请号：US18478121
申请日：2023-09-29
Applicant: Arm Limited
Inventor： Olof Henrik Uhrenholt , Andreas Due Engh-Halstvedt , Philip Carlos Garcia , Wing-Tsi Henry Wong , Sandeep Kala , Joseph Michael Richardson
IPC: G06T1/20
Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced.
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公开(公告)号：US12242856B2
公开(公告)日：2025-03-04
申请号：US17656346
申请日：2022-03-24
Applicant: Arm Limited
IPC: G06F9/38
Abstract: A data processor comprising an execution engine 51 for executing programs for execution threads and one or more caches 48, 49 operable to store data values for use when executing program instructions to perform processing operations for execution threads. The data processor further comprises a thread throttling control unit 54 configured to monitor the operation of the caches 48, 49 during execution of programs for execution threads, and to control the issuing of instructions for execution threads to the execution engine for executing a program based on the monitoring of the operation of the caches during execution of the program.
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公开(公告)号：US20240193719A1
公开(公告)日：2024-06-13
申请号：US18517191
申请日：2023-11-22
Applicant: Arm Limited
Inventor： Frank Klaeboe Langtind , Andreas Due Engh-Halstvedt
Abstract: A tiled-based graphics processor that comprises a plurality of tiling units is disclosed. The graphics processor includes an assigning circuit that assigns tiling units to process draw calls or draw call parts, and causes assigned tiling units to process draw calls or draw call parts.
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公开(公告)号：US20240169474A1
公开(公告)日：2024-05-23
申请号：US18503894
申请日：2023-11-07
Applicant: Arm Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Klaeboe Langtind
CPC classification number: G06T1/60 , G06F12/023 , G06T11/20
Abstract: When preparing and storing a primitive list in a tile-based graphics processing system, a first block of memory space is allocated for storing the primitive list. When there is insufficient space in the first block of memory space to store all of the graphics primitives for the primitive list, a next block of memory space to be used for storing the primitive list is allocated for storing the primitive list. An indication of the location in memory of the allocated next block of memory space is written at the beginning of the first block of memory space.
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公开(公告)号：US11210847B2
公开(公告)日：2021-12-28
申请号：US16697942
申请日：2019-11-27
Applicant: Arm Limited
Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. Associated state data for rendering the primitive is stored in a “state data” data structure in memory. For each region of the render output it is determined the primitive should be rendered for, a reference to the associated state data for rendering the primitive is stored in a respective, different data structure for each different region of the render output it is determined the primitive should be rendered for.
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Patent Agency Ranking
46.发明授权公开(公告)号：US11151034B2
公开(公告)日：2021-10-19
申请号：US16129560
申请日：2018-09-12
Applicant: Arm Limited
Inventor： Antonio García Guirado , Andreas Due Engh-Halstvedt
IPC: G06F12/08 , G06F12/0811 , G06F12/128 , G06F12/0895
Abstract: Cache storage comprising cache lines, each configured to store respective data entries. The cache storage is configured to store a tag in the form of: an individual tag portion which is individual to a cache line; a shareable tag portion which is shareable between cache lines; and pointer data which associates an individual tag portion with a shareable tag portion.
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公开(公告)号：US20210217131A1
公开(公告)日：2021-07-15
申请号：US16742556
申请日：2020-01-14
Applicant: Arm Limited
Inventor： Olof Henrik Uhrenholt , Andreas Due Engh-Halstvedt
IPC: G06T1/60 , G06F12/0875 , G06T1/20
Abstract: A data processing system includes a memory and a processor in communication with the memory. The processor is configured to, when storing an array of data in the memory, produce information representative of the content of a block of data representing a particular region of the array of data, write the block of data to a data structure in the memory, and write the information representative of the content of the block of data to the data structure.
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公开(公告)号：US11030783B1
公开(公告)日：2021-06-08
申请号：US16748712
申请日：2020-01-21
Applicant: Arm Limited
Abstract: A graphics processor that performs early depth tests for primitives in respect of patches of a render output, and depth tests for sampling positions of the render output, maintains a per patch depth buffer that stores depth values for patches for use by the patch early depth test and a per sample depth buffer. When processing of a render output is stopped before the render output is finished, the per sample depth values in the per sample depth buffer are written to storage so that those values can be restored, but the per patch depth value information in the per patch depth buffer is discarded. Then, when processing of the render output is resumed, the per sample depth buffer values are loaded into a per sample depth buffer, and the loaded per sample depth buffer values are also used to restore the per patch depth buffer.
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公开(公告)号：US20210158613A1
公开(公告)日：2021-05-27
申请号：US16697942
申请日：2019-11-27
Applicant: Arm Limited
Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. Associated state data for rendering the primitive is stored in a “state data” data structure in memory. For each region of the render output it is determined the primitive should be rendered for, a reference to the associated state data for rendering the primitive is stored in a respective, different data structure for each different region of the render output it is determined the primitive should be rendered for.
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公开(公告)号：US10580113B2
公开(公告)日：2020-03-03
申请号：US16153315
申请日：2018-10-05
Applicant: Arm Limited
Inventor： Lars Oskar Flordal , Toni Viki Brkic , Christian Vik Grovdal , Andreas Due Engh-Halstvedt , Frode Heggelund
Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
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