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公开(公告)号：US20250095571A1
公开(公告)日：2025-03-20
申请号：US18555023
申请日：2023-01-12
Inventor： Zhidong YUAN , Can YUAN , Dacheng ZHANG , Yongqian LI
IPC: G09G3/3233
Abstract: A display substrate and a display device are disclosed, the display substrate has a plurality of display partitions arranged in a plurality of rows and columns, and at least one display partition includes a plurality of sub-pixels; the display substrate includes a base substrate and common scanning signal lines, the common scanning signal lines are provided on the base substrate, and include a plurality of first common scanning signal lines extending along a first direction and a plurality of second common scanning signal lines extending along a second direction, and the first direction is different from the second direction; each of the plurality of second common scanning signal lines is electrically connected to one first common scanning signal line, and is configured to provide a common scanning signal to one display partition.
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公开(公告)号：US20240404476A1
公开(公告)日：2024-12-05
申请号：US18261113
申请日：2022-05-24
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN
IPC: G09G3/3266 , G09G3/3225
Abstract: A display substrate includes N groups of gate driving circuits and a multiplex circuit. Each group of gate driving circuits includes X gate driving circuits, and each gate driving circuit is electrically connected to rows of pixel circuits in a corresponding display zone. The X gate driving circuits are configured to output X scan signals of different functions to the rows of pixel circuits connected thereto. The multiplex circuit is electrically connected to N gate driving circuits of the N groups of gate driving circuits outputting scan signals of the same function, N selection control signal terminals and a start signal terminal. The multiplex circuit is configured to, under at least one selection control signal from at least one selection control signal terminal, select at least one group of gate driving circuits, and transmit a start signal from the start signal terminal to each selected group of gate driving circuits.
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公开(公告)号：US20240373687A1
公开(公告)日：2024-11-07
申请号：US18249359
申请日：2022-03-07
Inventor： Liu WU , Zhidong YUAN , Yongqian LI , Can YUAN
IPC: H10K59/131 , H10K59/10 , H10K59/121
Abstract: A profiled display panel, including a display area. The display area includes a plurality of display sub-areas; a plurality of cascade signal lines for coupling adjacent two of the gate driving sub-circuits. At least one cascade signal line includes a first cascade trace extending in a first direction and a second cascade trace extending in a second direction. The first cascade trace includes a plurality of first conductive patterns arranged on a first conductive layer and second conductive pattern arranged on a second conductive layer. The plurality of first conductive patterns are electrically connected to the second conductive pattern; and the second cascade trace includes a third conductive pattern arranged on the first conductive layer.
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公开(公告)号：US20240355286A1
公开(公告)日：2024-10-24
申请号：US18682942
申请日：2022-03-24
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Liu WU
IPC: G09G3/3233 , G11C19/28
CPC classification number: G09G3/3233 , G11C19/287 , G09G2300/0842 , G09G2310/0286 , G09G2310/08
Abstract: A display panel includes pixel driving circuits distributed in an array and forming pixel driving circuit groups, each pixel driving circuit group includes pixel driving circuit rows with each including pixel driving circuits, each of which includes a driving circuit connected to a first, second and third nodes, to input a driving current to the third node through the second node in response to a signal of the first node; a first switching unit with a first end connected to a first power supply terminal and second end connected to the second node, to connect the first power supply terminal and the second node in response to a pulse width modulation signal; in a same pixel driving circuit group, a second end of any first switching unit is connected to a second end of at least one first switching unit in each of the other pixel driving circuit rows.
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公开(公告)号：US20240268148A1
公开(公告)日：2024-08-08
申请号：US17914686
申请日：2021-11-18
Inventor： Zhidong YUAN , Pan XU , Jun LIU , Can YUAN , Yongqian LI
IPC: H10K59/121 , H10K59/12 , H10K59/131
CPC classification number: H10K59/1213 , H10K59/1201 , H10K59/1216 , H10K59/131
Abstract: A display panel includes a plurality of sub-pixels, a sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes at least a driving transistor and a storage capacitor. The display panel further includes a substrate, and a first gate conductive layer, a semiconductor layer and a second gate conductive layer that are disposed on the substrate. The first gate conductive layer includes a first electrode plate of the storage capacitor. The semiconductor layer includes an active layer pattern of the driving transistor. At least part of the active layer pattern of the driving transistor and at least part of the first electrode plate are disposed in a same layer. The second gate conductive layer includes a second electrode plate of the storage capacitor and a gate electrode of a driving transistor electrically connected to the second electrode plate.
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Patent Agency Ranking
公开(公告)号：US20240260343A1
公开(公告)日：2024-08-01
申请号：US18018550
申请日：2022-02-25
Inventor： Zhidong YUAN , Yongqian LI , Li SUN , Liu WU , Can YUAN
IPC: H10K59/131
CPC classification number: H10K59/131
Abstract: A display substrate and a display apparatus are provided, and the display substrate includes: a base substrate including a display area and a bonding area located at a side of the display area, the display area includes a first circuit signal line and a second circuit signal line, and the bonding area includes a bonding signal pin; a circuit structure layer located in the display area. The circuit structure layer includes at least one first circuit region and at least one second circuit region; the first circuit region includes at least one first gate drive circuit; the second circuit region includes at least one second gate drive circuit; the first gate drive circuit includes multiple cascaded first gate drive units, and the second gate drive circuit includes multiple cascaded second gate drive units; the multiple the first gate drive units are sequentially arranged along a second direction.
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公开(公告)号：US20240074266A1
公开(公告)日：2024-02-29
申请号：US18500345
申请日：2023-11-02
Inventor： Zhongyuan WU , Yongqian LI , Zhidong YUAN , Meng LI , Can YUAN
IPC: H10K59/131 , H10K50/824 , H10K50/828 , H10K50/86 , H10K59/122 , H10K59/124 , H10K71/00
CPC classification number: H10K59/1315 , H10K50/824 , H10K50/828 , H10K50/865 , H10K59/122 , H10K59/124 , H10K59/131 , H10K71/00 , H10K59/1201
Abstract: A display panel includes: a substrate, including a display area and a peripheral area surrounding the display area; an auxiliary electrode layer, located on a side of the substrate, where the auxiliary electrode layer includes an auxiliary electrode in the display area and a connection portion in the peripheral area; and a data line layer, including multiple data lines in the display area and a peripheral line portion in the peripheral area; where in the display area, the multiple data lines and the auxiliary electrode are provided in a same layer; and where in the peripheral area, the peripheral line portion and the connection portion are provided in a same layer.
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公开(公告)号：US20240046858A1
公开(公告)日：2024-02-08
申请号：US17641991
申请日：2021-05-18
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN
IPC: G09G3/3225
CPC classification number: G09G3/3225 , G09G2310/08
Abstract: The present disclosure provides a multiplexing circuitry, a multiplexing method, a multiplexing module, and a display device. The multiplexing circuitry includes N multiplexing unit circuitries, N energy storage unit circuitries and N control unit circuitries. An nth multiplexing unit circuitry is configured to enable an nth output data line to be electrically coupled to or electrically decoupled from an input data line under the control of a potential at an nth control end; an nth energy storage unit circuitry is configured to control a potential at the nth control end in accordance with an nth clock signal; and an nth control unit circuitry is configured to enable the nth control end to be electrically coupled to or electrically decoupled from an nth switch control line in accordance with a control voltage signal and an nth switch control signal.
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公开(公告)号：US20230260586A1
公开(公告)日：2023-08-17
申请号：US17417518
申请日：2020-12-29
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Wenchao BAO
IPC: G11C19/28 , G09G3/3266
CPC classification number: G11C19/28 , G09G3/3266 , G09G2310/0286
Abstract: The present disclosure provides a shift register unit, a driving method, a gate driving circuit and a display device. The shift register unit includes a pull-down node control circuit; the pull-down node control circuit is electrically connected to an input terminal, a reset terminal, a first voltage terminal, a second voltage terminal and a pull-down node, respectively, and is configured to, under the control of an input signal provided by the input terminal and a reset signal provided by the reset terminal, control the pull-down node to be electrically conducted to the first voltage terminal or the second voltage terminal, and control to hold a potential of the pull-down node.
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公开(公告)号：US20230091012A1
公开(公告)日：2023-03-23
申请号：US17439522
申请日：2021-02-09
Inventor： Zhidong YUAN , Yongqian LI , Meng LI , Can YUAN , Min HE , Chao JIAO
IPC: G09G3/3233
Abstract: This application relates to display panels, methods of driving the same, and display devices. The display panel includes: a first pixel circuit and a demultiplexing circuit. The first pixel circuit includes a first reset circuit, a first data writing circuit, and a first drive circuit. A first terminal of the first reset circuit is connected to a first terminal of the first drive circuit. A second terminal of the first reset circuit is connected to a first multiplexing signal line. A control terminal of the first drive circuit is connected to a first terminal of the first data writing circuit. A second terminal of the first data writing circuit is connected to the first multiplexing signal line. The demultiplexing circuit includes a first control circuit and a second control circuit. A first terminal of the first control circuit is connected to the first multiplexing signal line. A second terminal of the first control circuit is used for receiving a reset signal. A first terminal of the second control circuit is connected to the first multiplexing signal line. A second terminal of the second control circuit is used for receiving a first data signal.
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