公开(公告)号：US06251547B1

公开(公告)日：2001-06-26

申请号：US09422180

申请日：1999-10-22

申请人： San-De Tzu ,  Chia-Hui Lin ,  Wei-Zen Chou

发明人： San-De Tzu ,  Chia-Hui Lin ,  Wei-Zen Chou

IPC分类号： G03F900

CPC分类号： G03F1/29 ,  G03F1/32

摘要： A simple, cost-effective method for forming a lithography mask with a directly imaged portion and an attenuated, phase shifted portion. In particular, the use of such a method for forming an outrigger-type phase shift mask. The mask is formed on a blank consisting of a transparent quartz substrate over which is an attenuating phase shift layer and an optically opaque layer, by a process that produces a pattern in an E-beam sensitive resist with two different E-beam energy depositions. The higher energy deposition is used to form the main pattern, while the lower energy deposition forms the pattern for the outrigger.

摘要翻译： 用于形成具有直接成像部分和衰减的相移部分的光刻掩模的简单，成本有效的方法。 特别地，使用这种用于形成外伸支架型相移掩模的方法。 通过在具有两个不同电子束能量沉积的电子束敏感抗蚀剂中产生图案的工艺，将掩模形成在由透明石英基板构成的空白上，该透明石英基板是衰减相移层和光不透明层。 较高的能量沉积用于形成主图案，而较低的能量沉积形成外伸支架的图案。

公开(公告)号：US6077633A

公开(公告)日：2000-06-20

申请号：US210700

申请日：1998-12-14

申请人： Chia-Hui Lin ,  San-De Tzu

发明人： Chia-Hui Lin ,  San-De Tzu

IPC分类号： G03F1/32 ,  H01L21/768 ,  G03F9/00

CPC分类号： G03F1/32 ,  H01L21/76816

摘要： A mask and method of forming a mask for forming a closely spaced array of contact holes and larger isolated holes in an integrated circuit wafer. The mask provides a binary mask section for the formation of the closely spaced array of contact holes where the depth of focus is not a problem thereby avoiding problems due to side lobe effect. The mask also provides a ring type attenuating phase shifting mask for the formation of isolated larger holes where improved depth of focus is required, thereby also avoiding the problems due to side lobe effect in this region.

摘要翻译： 形成用于在集成电路晶片中形成紧密间隔的接触孔阵列和较大隔离孔的掩模的掩模和方法。 掩模提供用于形成紧密排列的接触孔阵列的二元掩模部分，其中聚焦深度不是问题，从而避免由于旁瓣效应引起的问题。 掩模还提供了一种用于形成隔离较大孔的环形衰减相移掩模，其中需要改善的焦深，从而也避免了由于该区域中的旁瓣效应引起的问题。

公开(公告)号：US6022644A

公开(公告)日：2000-02-08

申请号：US40335

申请日：1998-03-18

申请人： Chia-Hui Lin ,  San-De Tzu

发明人： Chia-Hui Lin ,  San-De Tzu

IPC分类号： G03F1/00 ,  G03F9/00

CPC分类号： G03F1/36

摘要： A electrical connection structure pattern according to the present invention includes a relatively dense first electrical connection structure area to a second electrical connection structure area. First, the electrical connection structure pattern is expensed to generate a first dummy pattern. The area of the first dummy pattern is larger than that of electrical connection structure pattern. Next, a second dummy pattern is generated by narrowing the line width of the first dummy pattern. A third dummy pattern is obtained by using CAD. The area of the third dummy pattern is smaller than that of the second dummy pattern, but larger than that of the electrical connection structure pattern. A fourth dummy pattern is generated by using CAD to remove the overlap area between the second dummy pattern and the third dummy pattern.

摘要翻译： 根据本发明的电连接结构图案包括与第二电连接结构区域相对致密的第一电连接结构区域。 首先，电连接结构图案被消耗以产生第一虚拟图案。 第一伪图案的面积大于电连接结构图案的面积。 接下来，通过使第一虚设图案的线宽变窄来生成第二虚设图案。 使用CAD获得第三个虚拟图案。 第三伪图案的面积小于第二虚设图案的面积，但是大于电连接结构图案的面积。 通过使用CAD来生成第四伪图案，以去除第二虚设图案和第三虚设图案之间的重叠区域。

公开(公告)号：US5994009A

公开(公告)日：1999-11-30

申请号：US971541

申请日：1997-11-17

申请人： San-De Tzu ,  Shih-Chiang Tu ,  Chia-Hui Lin

发明人： San-De Tzu ,  Shih-Chiang Tu ,  Chia-Hui Lin

IPC分类号： G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F9/70

摘要： The present invention discloses a novel method for interlayer corrections for photolithographic patterns that are reproduced on a wafer surface capable of correcting not only the optically-induced proximity effect but also the process-induced proximity effect. In the method, a conventional optical proximity correction is first performed on a photomask, the corrected photomask is then used to produce a pattern on a wafer surface. The various critical dimensions bias values at a multiplicity of locations are then measured and fed back to the computer aided design data file for the photomask for producing patterns that are corrected for both optically-induced and process-induced proximity effect on a wafer surface.

摘要翻译： 本发明公开了一种用于光刻图案的层间校正的新颖方法，其在不仅能够校正光学感应的接近效应而且可以校正处理引起的接近效应的晶片表面上再现。 在该方法中，首先在光掩模上执行传统的光学邻近校正，然后使用经校正的光掩模在晶片表面上产生图案。 然后测量多个位置处的各种临界尺寸偏差值，并将其反馈给用于光掩模的计算机辅助设计数据文件，以产生针对晶片表面上的光学诱导和处理诱导的接近效应校正的图案。

公开(公告)号：US5559534A

公开(公告)日：1996-09-24

申请号：US506958

申请日：1995-07-28

申请人： Chia-Hui Lin

发明人： Chia-Hui Lin

IPC分类号： G06F3/033 ,  G09G3/02

CPC分类号： G06F3/0312 ,  G06F3/03543 ,  G06F2203/0333

摘要： An improved photoelectric sensor for an X-Y input device, the input device including vertical and horizontal slotted discs at ends of respective vertical and horizontal shafts, the discs being situated adjacent but not touching one another, is made up of a single photoelectric sensor and a single LED installed on opposite sides of the portions of the slotted discs that are adjacent each other, with the photosensor including four photoelectric sensor areas A, B, C, and D located on a single chip and having a width corresponding to the width of a slot or slotted wall of the slotted disc such that the rotation direction of the respective discs can be determined by whether the phase difference between signals generated by sensors A and B, and between signals generated by sensors C and D, is positive or negative.

摘要翻译： 一种用于XY输入装置的改进的光电传感器，该输入装置包括垂直和水平开槽的圆盘，各个垂直和水平轴的端部相邻但不相互接触的光盘由单个光电传感器和单个光电传感器组成 LED安装在彼此相邻的开槽盘的部分的相对侧上，光电传感器包括位于单个芯片上的四个光电传感器区域A，B，C和D，其宽度对应于槽的宽度 或槽槽的开槽壁，使得各个盘的旋转方向可以由传感器A和B产生的信号之间以及由传感器C和D产生的信号之间的相位差是正还是负来确定。