公开(公告)号：US06294295B1

公开(公告)日：2001-09-25

申请号：US09519612

申请日：2000-03-06

申请人： Chia-Hui Lin ,  San-De Tzu ,  Wei-Zen Chou

发明人： Chia-Hui Lin ,  San-De Tzu ,  Wei-Zen Chou

IPC分类号： G03F900

CPC分类号： G03F1/32 ,  G03F1/26 ,  G03F1/29

摘要： This invention describes an attenuating phase shifting mask, a method of forming the attenuating phase shifting mask, and a method of using the attenuating phase shifting mask to expose a contact hole pattern having both dense and isolated contact holes on a layer of photosensitive dielectric. The mask has a rim of first attenuating phase shifting material, having a first transmittance and providing a phase shift of 180°, surrounding the dense holes and a rim of second attenuating phase shifting material, having a second transmittance and providing a phase shift of 180°, surrounding the isolated holes. The second transmittance is greater than the first transmittance. The dense holes have a duty ratio of less than 2.0 and the isolated holes have a duty ratio of greater than or equal to 2.0. The second attenuating phase shifting material results from treating the first attenuating phase shifting material for a first time with a first solution which increases the transmittance and changes the phase shift. The attenuating phase shifting material is then treated with a second solution for a second time to restore the phase shift to 180° and further increase the transmittance.

摘要翻译： 本发明描述了衰减相移掩模，形成衰减相移掩模的方法，以及使用衰减相移掩模来曝光在光敏电介质层上具有密集和隔离接触孔的接触孔图案的方法。 掩模具有第一衰减相移材料的边缘，具有第一透射率并且提供180°的相移，围绕致密孔和第二衰减相移材料的边缘，具有第二透射率并提供180°的相移 °，围绕隔离孔。 第二透射率大于第一透射率。 密孔的占空比小于2.0，隔离孔的占空比大于或等于2.0。 第二衰减相移材料是通过用提高透射率并改变相移的第一溶液第一次处理第一衰减相移材料产生的。 然后衰减相移材料用第二溶液处理第二次以将相移恢复到180°并进一步增加透射率。

公开(公告)号：US06251547B1

公开(公告)日：2001-06-26

申请号：US09422180

申请日：1999-10-22

申请人： San-De Tzu ,  Chia-Hui Lin ,  Wei-Zen Chou

发明人： San-De Tzu ,  Chia-Hui Lin ,  Wei-Zen Chou

IPC分类号： G03F900

CPC分类号： G03F1/29 ,  G03F1/32

摘要： A simple, cost-effective method for forming a lithography mask with a directly imaged portion and an attenuated, phase shifted portion. In particular, the use of such a method for forming an outrigger-type phase shift mask. The mask is formed on a blank consisting of a transparent quartz substrate over which is an attenuating phase shift layer and an optically opaque layer, by a process that produces a pattern in an E-beam sensitive resist with two different E-beam energy depositions. The higher energy deposition is used to form the main pattern, while the lower energy deposition forms the pattern for the outrigger.

摘要翻译： 用于形成具有直接成像部分和衰减的相移部分的光刻掩模的简单，成本有效的方法。 特别地，使用这种用于形成外伸支架型相移掩模的方法。 通过在具有两个不同电子束能量沉积的电子束敏感抗蚀剂中产生图案的工艺，将掩模形成在由透明石英基板构成的空白上，该透明石英基板是衰减相移层和光不透明层。 较高的能量沉积用于形成主图案，而较低的能量沉积形成外伸支架的图案。

公开(公告)号：US06301698B1

公开(公告)日：2001-10-09

申请号：US09387434

申请日：1999-09-01

申请人： Chia-Hui Lin ,  San-De Tzu

发明人： Chia-Hui Lin ,  San-De Tzu

IPC分类号： G06F1750

CPC分类号： G03F1/32 ,  G03F1/29 ,  G03F1/34

摘要： A method is described for using computer aided design data for contact holes in a background, such as an opaque background or a phase shifting background, to generate computer aided design data for fabricating a mask an outrigger pattern. The outrigger pattern mask has contact holes surrounded by a first border of opaque material and the first border of opaque material surrounded by a third border of attenuating or 100% transmittance phase shifting material. The third border of attenuating or 100% transmittance phase shifting material is surrounded by opaque material. The design data for the contact hole pattern, a background pattern, a first correction pattern, and a second correction pattern are combined in a computer processor to generate final data. The final data is used to fabricate the mask.

摘要翻译： 描述了一种方法，用于使用计算机辅助设计数据用于背景中的接触孔，例如不透明背景或相移背景，以产生用于制造掩模外伸支架图案的计算机辅助设计数据。 外伸支架图案掩模具有被不透明材料的第一边界包围的接触孔和由衰减或100％透射相移材料的第三边界包围的不透明材料的第一边界。 衰减或100％透光相移材料的第三个边界被不透明材料包围。 接触孔图案的设计数据，背景图案，第一校正图案和第二校正图案被组合在计算机处理器中以产生最终数据。 最终的数据用于制作掩码。

公开(公告)号：US06174801B1

公开(公告)日：2001-01-16

申请号：US09261997

申请日：1999-03-05

申请人： San-De Tzu ,  Ching-Shiun Chiu ,  Chia-Hui Lin

发明人： San-De Tzu ,  Ching-Shiun Chiu ,  Chia-Hui Lin

IPC分类号： H01L214763

CPC分类号： H01L21/76807 ,  G03F7/2059 ,  H01L21/02063 ,  H01L21/0277 ,  H01L21/3081 ,  H01L21/3086 ,  H01L2221/1021

摘要： A method is disclosed for employing direct electron beam writing in the lithography used for forming step-profiles in semiconductor devices. The number of steps in the profiles are not limited. An electron beam sensitive resist is formed over a substrate. The resist is then exposed to a scanning electron beam having precise information, including proximity effect correction data, to directly form stair-case-like openings in the resist. The highly accurately dimensioned step-profiles are then transferred into the underlying layers by performing appropriate etchings. The resulting structures are shown to be especially suitable for forming damascene interconnects for submicron technologies.

摘要翻译： 公开了一种在用于在半导体器件中形成阶梯轮廓的光刻中采用直接电子束写入的方法。 配置文件中的步骤数不受限制。 在衬底上形成电子束敏感抗蚀剂。 然后将抗蚀剂暴露于具有精确信息的扫描电子束，包括邻近效应校正数据，以直接在抗蚀剂中形成阶梯状开口。 然后通过执行适当的蚀刻将高度精确尺寸的阶梯轮廓转移到下面的层中。 所得到的结构显示出特别适用于形成亚微米技术的镶嵌互连。

公开(公告)号：US6051347A

公开(公告)日：2000-04-18

申请号：US270595

申请日：1999-03-18

申请人： San-De Tzu ,  Chia-Hui Lin

发明人： San-De Tzu ,  Chia-Hui Lin

IPC分类号： G03F7/20 ,  G03C5/00

CPC分类号： G03F7/70441 ,  Y10S430/143

摘要： A method of correcting, or compensating for errors encountered in the transfer of patterns is disclosed for use with high resolution e-beam lithography. In a first embodiment, optical proximity effects are incorporated into the e-beam proximity effects by superimposing the two effects to arrive at a compensated dosage level database to produce the desired patterns. In a second embodiment, etching effects are also superimposed on the previous driving database by compensating the e-beam proximity data twice, that is, by over correcting it, to further improve the transfer of patterns without the undesirable effects. It is shown that corrections for a number of other process steps can also be incorporated into the database that drives the e-beam lithography machine in order to achieve high resolution patterns of about one-quarter-micron technology.

摘要翻译： 公开了一种校正或补偿在图案传送中遇到的错误的方法，用于高分辨率电子束光刻。 在第一实施例中，通过叠加两个效应来将光学邻近效应并入到电子束邻近效应中，以得到补偿剂量水平数据库以产生期望的图案。 在第二实施例中，通过补偿电子束邻近数据两次，即通过对其进行过度校正，也可以对先前的驱动数据库叠加蚀刻效果，以进一步改善图案的传送而不产生不良影响。 显示出许多其他工艺步骤的校正也可以并入驱动电子束光刻机的数据库中，以实现约四分之一微米技术的高分辨率图案。

公开(公告)号：US5888678A

公开(公告)日：1999-03-30

申请号：US20502

申请日：1998-02-09

申请人： San-De Tzu ,  Chia-Hui Lin ,  Wen-Hong Huang ,  Ching-Chia Lin

发明人： San-De Tzu ,  Chia-Hui Lin ,  Wen-Hong Huang ,  Ching-Chia Lin

IPC分类号： G03F1/00 ,  G03F1/29 ,  G03F9/00

CPC分类号： G03F1/29

摘要： A mask and a method of forming a mask having a binary mask pattern in a first region of a transparent mask substrate and a rim type attenuating phase shifting mask pattern in a second region of the same transparent mask substrate. The rim type attenuating phase shifting mask pattern is used to form small contact holes and the binary mask pattern is used to form larger contact holes in an integrated circuit wafer. The use of the rim type attenuating phase shifting mask pattern and the binary mask pattern avoids the problems due to side lobe effect for cases where different size contact holes are required on the same layer in an integrated circuit wafer. The formation of the rim type attenuating phase shifting mask pattern and the binary mask pattern on the same transparent mask substrate increases throughput and decreases cost in the fabrication of integrated circuit wafers.

摘要翻译： 在相同的透明掩模基板的第二区域中，在透明掩模基板的第一区域中形成具有二元掩模图案的掩模和边缘型衰减相移掩模图案的掩模和方法。 边缘型衰减相移掩模图案用于形成小的接触孔，并且二进制掩模图案用于在集成电路晶片中形成更大的接触孔。 使用边缘型衰减相移掩模图案和二进制掩模图案避免了在集成电路晶片的同一层上需要不同尺寸的接触孔的情况下由于旁瓣效应引起的问题。 在相同的透明掩模基板上形成边缘型衰减相移掩模图案和二进制掩模图案增加了集成电路晶片的制造中的吞吐量并降低了成本。

公开(公告)号：US5783337A

公开(公告)日：1998-07-21

申请号：US856786

申请日：1997-05-15

申请人： San-De Tzu ,  Chih-Chiang Tu ,  Wen-Hong Huang ,  Chia-Hui Lin

发明人： San-De Tzu ,  Chih-Chiang Tu ,  Wen-Hong Huang ,  Chia-Hui Lin

IPC分类号： G03F1/32 ,  G03F9/00

CPC分类号： G03F1/32

摘要： A new process for fabricating an attenuated phase-shifting photomask is described. A photomask blank is provided comprising a phase-shifting layer overlying a substrate, a chromium layer overlying the phase-shifting layer, and a resist layer overlying the chromium layer. The resist layer of the photomask blank is exposed to electron-beam energy wherein a main pattern area of the photomask blank is exposed to a first dosage of the electron-beam energy and wherein a border area surrounding the main pattern area is not exposed to the electron-beam energy and wherein a secondary pattern area between the main pattern area and the border area is exposed to a second dosage of electron-beam energy wherein the second dosage is lower than the first dosage. The exposed resist layer is developed wherein the resist within the main pattern area is removed to expose the chromium layer. The exposed chromium layer is etched through to expose the underlying phase-shifting layer. The exposed phase-shifting layer is etched through to expose the substrate. The resist overlying the chromium layer within the secondary pattern area is etched away. The chromium layer within the secondary pattern area is etched away. The resist within the border area is stripped away to leave a patterned phase-shifting layer in the main pattern area and a chromium layer in the border area to complete fabrication of the attenuated phase-shifting photomask.

摘要翻译： 描述了制造衰减相移光掩模的新工艺。 提供了一种光掩模坯料，其包括覆盖衬底的相移层，覆盖在相移层上的铬层和覆盖在铬层上的抗蚀剂层。 光掩模坯料的抗蚀剂层暴露于电子束能量，其中光掩模坯料的主图案区域暴露于第一剂量的电子束能量，并且其中围绕主图案区域的边界区域不暴露于 电子束能量，其中主图案区域和边界区域之间的次级图案区域暴露于第二剂量的电子束能量，其中第二剂量低于第一剂量。 显影曝光的抗蚀剂层，其中去除主图案区域内的抗蚀剂以暴露铬层。 暴露的铬层被蚀刻通过以暴露下面的相移层。 暴露的相移层被蚀刻以暴露衬底。 覆盖二次图案区域内的铬层的抗蚀剂被蚀刻掉。 二次图案区域内的铬层被蚀刻掉。 边界区域内的抗蚀剂被剥离，在主图案区域中留下图案化的相移层和边界区域中的铬层，以完成衰减的相移光掩模的制造。

公开(公告)号：US6077633A

公开(公告)日：2000-06-20

申请号：US210700

申请日：1998-12-14

申请人： Chia-Hui Lin ,  San-De Tzu

发明人： Chia-Hui Lin ,  San-De Tzu

IPC分类号： G03F1/32 ,  H01L21/768 ,  G03F9/00

CPC分类号： G03F1/32 ,  H01L21/76816

摘要： A mask and method of forming a mask for forming a closely spaced array of contact holes and larger isolated holes in an integrated circuit wafer. The mask provides a binary mask section for the formation of the closely spaced array of contact holes where the depth of focus is not a problem thereby avoiding problems due to side lobe effect. The mask also provides a ring type attenuating phase shifting mask for the formation of isolated larger holes where improved depth of focus is required, thereby also avoiding the problems due to side lobe effect in this region.

摘要翻译： 形成用于在集成电路晶片中形成紧密间隔的接触孔阵列和较大隔离孔的掩模的掩模和方法。 掩模提供用于形成紧密排列的接触孔阵列的二元掩模部分，其中聚焦深度不是问题，从而避免由于旁瓣效应引起的问题。 掩模还提供了一种用于形成隔离较大孔的环形衰减相移掩模，其中需要改善的焦深，从而也避免了由于该区域中的旁瓣效应引起的问题。

公开(公告)号：US6022644A

公开(公告)日：2000-02-08

申请号：US40335

申请日：1998-03-18

申请人： Chia-Hui Lin ,  San-De Tzu

发明人： Chia-Hui Lin ,  San-De Tzu

IPC分类号： G03F1/00 ,  G03F9/00

CPC分类号： G03F1/36

摘要： A electrical connection structure pattern according to the present invention includes a relatively dense first electrical connection structure area to a second electrical connection structure area. First, the electrical connection structure pattern is expensed to generate a first dummy pattern. The area of the first dummy pattern is larger than that of electrical connection structure pattern. Next, a second dummy pattern is generated by narrowing the line width of the first dummy pattern. A third dummy pattern is obtained by using CAD. The area of the third dummy pattern is smaller than that of the second dummy pattern, but larger than that of the electrical connection structure pattern. A fourth dummy pattern is generated by using CAD to remove the overlap area between the second dummy pattern and the third dummy pattern.

摘要翻译： 根据本发明的电连接结构图案包括与第二电连接结构区域相对致密的第一电连接结构区域。 首先，电连接结构图案被消耗以产生第一虚拟图案。 第一伪图案的面积大于电连接结构图案的面积。 接下来，通过使第一虚设图案的线宽变窄来生成第二虚设图案。 使用CAD获得第三个虚拟图案。 第三伪图案的面积小于第二虚设图案的面积，但是大于电连接结构图案的面积。 通过使用CAD来生成第四伪图案，以去除第二虚设图案和第三虚设图案之间的重叠区域。

公开(公告)号：US5994009A

公开(公告)日：1999-11-30

申请号：US971541

申请日：1997-11-17

申请人： San-De Tzu ,  Shih-Chiang Tu ,  Chia-Hui Lin

发明人： San-De Tzu ,  Shih-Chiang Tu ,  Chia-Hui Lin

IPC分类号： G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F9/70

摘要： The present invention discloses a novel method for interlayer corrections for photolithographic patterns that are reproduced on a wafer surface capable of correcting not only the optically-induced proximity effect but also the process-induced proximity effect. In the method, a conventional optical proximity correction is first performed on a photomask, the corrected photomask is then used to produce a pattern on a wafer surface. The various critical dimensions bias values at a multiplicity of locations are then measured and fed back to the computer aided design data file for the photomask for producing patterns that are corrected for both optically-induced and process-induced proximity effect on a wafer surface.

摘要翻译： 本发明公开了一种用于光刻图案的层间校正的新颖方法，其在不仅能够校正光学感应的接近效应而且可以校正处理引起的接近效应的晶片表面上再现。 在该方法中，首先在光掩模上执行传统的光学邻近校正，然后使用经校正的光掩模在晶片表面上产生图案。 然后测量多个位置处的各种临界尺寸偏差值，并将其反馈给用于光掩模的计算机辅助设计数据文件，以产生针对晶片表面上的光学诱导和处理诱导的接近效应校正的图案。