公开(公告)号：US5822247A

公开(公告)日：1998-10-13

申请号：US775111

申请日：1996-12-30

Applicant: Fabio Tassan Caser ,  Corrado Villa ,  Simone Bartoli

Inventor： Fabio Tassan Caser ,  Corrado Villa ,  Simone Bartoli

IPC: G11C5/14 ,  G11C8/08 ,  G11C16/16 ,  G11C16/30 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C5/147 ,  G11C8/08

Abstract: The present invention relates to a device for generating and regulating a gate voltage in an electrically programmable non-volatile memory with single power supply of the type comprising a voltage booster driven by a clock signal applied to a first input terminal thereof and having an output terminal on which is produced a signal with higher voltage. This device comprises a lower regulator block and a programming switching block inserted in parallel each other between said output terminal of the voltage booster and an output terminal of the gate voltage generating and regulating device with said lower regulator block being driven by a plurality of switching signals to supply on the output terminal of the device a plurality of regulated voltages and feed the control gates of the non-volatile memory cells.

Abstract translation: 本发明涉及一种用于在电可编程非易失性存储器中产生和调节栅极电压的装置，该单电源包括由施加到其第一输入端的时钟信号驱动的升压驱动器，并具有输出端 在其上产生具有较高电压的信号。 该装置包括在升压器的所述输出端子和栅极电压产生和调节装置的输出端子之间并联插入的下调节器块和编程切换块，所述下调节器块由多个开关信号驱动 在装置的输出端子上提供多个调节电压并馈送非易失性存储单元的控制栅极。

公开(公告)号：US5719807A

公开(公告)日：1998-02-17

申请号：US687257

申请日：1996-07-25

Applicant: Mauro Sali ,  Corrado Villa ,  Marcello Carrera

Inventor： Mauro Sali ,  Corrado Villa ,  Marcello Carrera

IPC: G11C16/08 ,  G11C11/34

CPC classification number: G11C16/08

Abstract: A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.