公开(公告)号：US6112258A

公开(公告)日：2000-08-29

申请号：US44291

申请日：1998-03-19

申请人： David S. Miller ,  Kenneth J. DeLong

发明人： David S. Miller ,  Kenneth J. DeLong

IPC分类号： G06F13/364 ,  G06F13/00

CPC分类号： G06F13/364

摘要： An arbiter circuit is employed to isolate a processor from a plurality of Input/Output Application Specific Integrated Circuits ("I/O ASICs"). The processor is coupled to the arbiter through a control bus, an address bus and a data bus. The arbiter is coupled to the I/O ASICs through an extension of the control bus and a combined address/data bus. The arbiter manages control of the control bus extension and address/data bus to enable contemporaneous transmission ("broadcast") of messages to the I/O ASICs, and enable the processor to access the I/O ASICs. Only one of the I/O ASICs is granted control of the control bus extension and address/data bus at any point in time. The processor may also be granted sole control of the control bus extension and address/data bus.

摘要翻译： 采用仲裁电路将处理器与多个输入/输出专用集成电路（“I / O ASIC”）隔离开来。 处理器通过控制总线，地址总线和数据总线耦合到仲裁器。 仲裁器通过控制总线的扩展和组合的地址/数据总线耦合到I / O ASIC。 仲裁器管理控制总线扩展和地址/数据总线的控制，以实现向I / O ASIC同时传输（“广播”）消息，并使处理器能够访问I / O ASIC。 只有其中一个I / O ASIC被授权在任何时间点控制总线扩展和地址/数据总线。 处理器也可以被授予对控制总线扩展和地址/数据总线的唯一控制。

公开(公告)号：US5777990A

公开(公告)日：1998-07-07

申请号：US838240

申请日：1997-04-16

申请人： Ephraim Zehavi ,  David S. Miller ,  Judith LaRocca

发明人： Ephraim Zehavi ,  David S. Miller ,  Judith LaRocca

IPC分类号： H04B7/216 ,  H04J11/00 ,  H04J13/00 ,  H04J13/16 ,  H04L1/00 ,  H04L7/02 ,  H04L9/22 ,  H04J13/04

CPC分类号： H04L1/0071 ,  H04J13/0048 ,  H04J13/16

摘要： A variable rate transmission system where a packet of variable is transmitted on a traffic channel if the capacity of the traffic channel is greater than or equal to the data rate of the packet. When the rate of the packet of variable rate data exceeds the capacity of the traffic channel, the packet is transmitted on a traffic channel and at least one overflow channel. Also described is a receiving system for receiving and reassembling the data transmitted on the traffic channel and at least one additional overflow channels.

摘要翻译： 如果业务信道的容量大于或等于分组的数据速率，则在业务信道上发送变量分组的可变速率传输系统。 当可变速率数据的分组的速率超过业务信道的容量时，分组在业务信道和至少一个溢出信道上发送。 还描述了一种用于接收和重新组合在业务信道上发送的数据和至少一个附加溢出信道的接收系统。

公开(公告)号：US5608722A

公开(公告)日：1997-03-04

申请号：US415958

申请日：1995-04-03

申请人： David S. Miller

发明人： David S. Miller

IPC分类号： H04J13/04 ,  H04B7/08 ,  H04B7/216 ,  H04B7/26

CPC分类号： H04B7/0891 ,  H04B7/0845 ,  H04B7/216 ,  H04B7/2628

摘要： Method and apparatus for receiving signals in gateways for satellite repeater type spread spectrum communication systems making more efficient use of data transfer capacity and diversity processing. Several communication signals are received by multiple analog receivers and converted into digital format. The digital communication signals are transferred from each analog receiver into a series of demodulation or FHT modules in which they are first despread into encoded data symbols using predetermined PN coding sequences, and then mapped into symbol energy metrics using orthogonal transformers, such as fast Hadamard transformers. The transformation output for each communication channel from each analog receiver is input to a single metric receiver for a data channel or subscriber, where it is subjected to conventional metric signal processing to reconstruct the data. A set of dedicated modules is coupled to each analog receiver for handling each diversity path or subscriber active communication system channel being transferred through that receiver or analog path. Each demodulation or FHT module comprises despreading elements and FHT components that are easily distributed in processing arrays within the gateway.

摘要翻译： 用于在卫星中继器类型扩频通信系统的网关中接收信号的方法和装置，从而更有效地利用数据传输容量和分集处理。 多个通信信号被多个模拟接收机接收并转换为数字格式。 数字通信信号从每个模拟接收机传送到一系列解调或FHT模块，其中它们首先使用预定的PN编码序列解扩展成编码数据符号，然后使用正交变换器（例如快速的哈达马特变换器）映射到符号能量度量 。 来自每个模拟接收机的每个通信信道的变换输出被输入到用于数据信道或用户的单个度量接收机，在那里它经受常规度量信号处理以重构数据。 一组专用模块耦合到每个模拟接收机，用于处理通过该接收机或模拟路径传送的每个分集路径或用户主动通信系统信道。 每个解调或FHT模块包括易于分布在网关内的处理阵列中的解扩元件和FHT组件。