公开(公告)号：US06376286B1

公开(公告)日：2002-04-23

申请号：US09421305

申请日：1999-10-20

申请人： Dong-Hyuk Ju

发明人： Dong-Hyuk Ju

IPC分类号： H01L2976

CPC分类号： H01L27/1203 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/84

摘要： A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

摘要翻译： 在常规体硅晶片上形成绝缘体上硅（SOI）场效应晶体管（FET）结构。 该结构包括FET与沟槽区域之间的电耦合，以消除由于FET的历史操作导致的沟道区域中的电荷累积引起的浮体效应。 形成结构的方法包括通过在FET的周边形成绝缘沟槽并在有源区下方形成底切以在源极和漏极区域之间形成底切，从而将FET有源区与硅衬底中的其它结构隔离开来 和硅衬底。

公开(公告)号：US06232208B1

公开(公告)日：2001-05-15

申请号：US09187428

申请日：1998-11-06

申请人： David Wu ,  Dong-Hyuk Ju

发明人： David Wu ,  Dong-Hyuk Ju

IPC分类号： H01L213205

CPC分类号： H01L29/4916 ,  H01L21/28035 ,  H01L21/82385 ,  H01L29/42376 ,  H01L29/6659

摘要： A semiconductor device is provided with a gate electrode having a substantially rectangular profile by depositing a layer of amorphous or microcrystalline silicon. The amorphous or microcrystalline silicon is doped with impurities, before patterning to form the gate electrode, to reduce gate depletion. The doped gate electrode layer is then patterned to form a gate electrode having a substantially rectangular profile.

摘要翻译： 通过沉积非晶或微晶硅层，半导体器件设置有具有基本上矩形轮廓的栅电极。 在构图形成栅电极之前，非晶或微晶硅掺杂有杂质，以减少栅极耗尽。 然后对掺杂的栅电极层进行构图以形成具有大致矩形轮廓的栅电极。

公开(公告)号：US06232166B1

公开(公告)日：2001-05-15

申请号：US09187523

申请日：1998-11-06

申请人： Dong-Hyuk Ju ,  Scott Luning

发明人： Dong-Hyuk Ju ,  Scott Luning

IPC分类号： H01L218238

CPC分类号： H01L29/66537 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

摘要： Halo implant regions are formed in a P-channel semiconductor device employing a zero degree tilt angle. N-type impurities are ion implanted to the desired depth in the semiconductor substrate prior to forming P-channel lightly doped source/drain areas. Subsequently, moderately or heavily doped source/drain regions are formed, followed by activation annealing. The halo implants diffuse to form halo structures at the desired location, thereby reducing short channel effects, such as subsurface punchthrough. Other embodiments enable independent control of the junction depths and channel lengths of N- and P-channel transistors, while maintaining high manufacturing throughput.

摘要翻译： 卤素注入区域形成在采用零度倾斜角的P沟道半导体器件中。 在形成P沟道轻掺杂的源极/漏极区之前，将N型杂质离子注入半导体衬底中所需的深度。 随后，形成适度或重掺杂的源极/漏极区，随后进行激活退火。 光晕植入物在期望的位置扩散以形成晕圈结构，从而减少短通道效应，例如地下穿孔。 其他实施例能够独立控制N沟道晶体管和P沟道晶体管的结深度和沟道长度，同时保持高的制造吞吐量。

公开(公告)号：US5972760A

公开(公告)日：1999-10-26

申请号：US924639

申请日：1997-09-05

申请人： Dong-Hyuk Ju

发明人： Dong-Hyuk Ju

IPC分类号： H01L21/265 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  Y10S438/976

摘要： Shallow LDD junctions are obtained by depositing a thin screening oxide layer prior to moderate or heavy ion implantations. The use of a thin deposited screening oxide, as by plasma enhanced chemical vapor deposition, instead of a thermally grown oxide, minimizes transient enhanced diffusion during annealing to activate the source/drain regions, thereby decreasing the junction depth.

摘要翻译： 通过在中等或重离子注入之前沉积薄的筛选氧化物层，获得浅的LDD结。 使用薄的沉积屏蔽氧化物，如通过等离子体增强化学气相沉积而不是热生长的氧化物，在退火期间使瞬态增强的扩散最小化，以激活源极/漏极区域，从而降低结深度。

公开(公告)号：US5846857A

公开(公告)日：1998-12-08

申请号：US924637

申请日：1997-09-05

申请人： Dong-Hyuk Ju

发明人： Dong-Hyuk Ju

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823864

摘要： N- and P-channel transistor characteristics are independently optimized for CMOS semiconductor devices with design features of 0.25 microns and under. Removable second sidewall spacers are formed on the N-channel transistor gate electrode having first sidewall spacers thereon. Ion implantation is conducted to form N-type moderately/heavily doped implants followed by activation annealing. The second sidewall spacer is then removed from the P-channel transistor leaving first sidewall spacers thereon serving as an ion implantation mask for the P-type lightly doped implants. Subsequently, third sidewall spacers are formed on the P-channel gate electrode having first sidewall spacers thereon followed by ion implantation to form the P-type moderately or heavily doped implants, with subsequent activation annealing. Embodiments enable complete independent control of the channel lengths of the N- and P-channel transistors by varying the width of the first, second and third sidewall spacers.

摘要翻译： 针对具有0.25微米及以下设计特征的CMOS半导体器件独立优化了N沟道和P沟道晶体管特性。 可移动的第二侧壁间隔物形成在其上具有第一侧壁间隔物的N沟道晶体管栅电极上。 进行离子注入以形成N型中等/重掺杂的植入物，然后进行活化退火。 然后将第二侧壁间隔物从P沟道晶体管除去，留下第一侧壁间隔物，其用作P型轻掺杂植入物的离子注入掩模。 随后，在其上具有第一侧壁间隔物的P沟道栅电极上形成第三侧壁间隔物，然后进行离子注入以形成P型适度或重掺杂的植入物，随后进行激活退火。 实施例通过改变第一，第二和第三侧壁间隔物的宽度能够完全独立地控制N沟道晶体管和P沟道晶体管的沟道长度。