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    APPARATUS AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
    42.
    发明申请
    APPARATUS AND METHOD FOR CONTROLLING NONVOLATILE MEMORY 有权

    公开(公告)号：US20250013378A1

    公开(公告)日：2025-01-09

    申请号：US18587463

    申请日：2024-02-26

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Suk-Ho LEE ,  Kyu-Seung HAN ,  Jae-Jin LEE

    IPC: G06F3/06

    Abstract: Disclosed herein is an apparatus and method for controlling nonvolatile memory. The apparatus may include nonvolatile memory and a memory controller for issuing a serial clock (SCK) to the nonvolatile memory and transferring data corresponding to a requested command to the nonvolatile memory or receiving data corresponding to a requested command from the nonvolatile memory and outputting the data to the outside through a serial-in or a serial-out in response to a read request or a write request.

    SPIKING NEURAL NETWORK CIRCUITS GENERATING SPIKE SIGNALS AND METHOD OF OPERATION THEREOF
    43.
    发明申请
    SPIKING NEURAL NETWORK CIRCUITS GENERATING SPIKE SIGNALS AND METHOD OF OPERATION THEREOF 有权

    公开(公告)号：US20240428047A1

    公开(公告)日：2024-12-26

    申请号：US18422776

    申请日：2024-01-25

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Tae Wook KANG ,  Hyuk KIM ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N3/063

    Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates first and second input spike signals, a synapse circuit that generates a first current based on the first input spike signal and a weight and generates a second current based on the second input spike signal and the weight, a capacitor that forms a first membrane voltage based on the first current, and a neuron circuit including a comparator and that resets the first membrane voltage, and after the capacitor further forms a second membrane voltage based on the second current, and the comparator includes a first input terminal and a second input terminal, receives the first membrane voltage through the first input terminal and a reference voltage through the second input terminal, generates a first spike signal based on a first comparison operation of the first membrane voltage and the reference voltage.

    ENCODER AND OPERATION METHOD THEREOF
    47.
    发明申请
    ENCODER AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20230125421A1

    公开(公告)日：2023-04-27

    申请号：US17893815

    申请日：2022-08-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Tae Wook KANG ,  Sung Eun KIM ,  Kyung Jin BYUN ,  Kwang IL OH ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N10/20

    Abstract: Disclosed is operation method of an encoder that receives a continuous time-series signal and respectively transmits first to N-th input signals to first to N-th input neuron circuits of spike neural network circuit. The method of operating the encoder includes receiving the continuous time-series signal, generating a plurality of discrete quantum signals by sampling and quantizing the continuous time-series signal, selecting first to N-th discrete quantum signals among the plurality of discrete quantum signals, matching the selected first to N-th discrete quantum signals with the first to N-th input neuron circuits, respectively, identifying discrete quantum signals, each of which has a quantum level different from a quantum level of a previous discrete quantum signal, from among the second to N-th discrete quantum signals, and activating the input signals to be transmitted to the input neuron circuits corresponding to the identified discrete quantum signals and the first discrete quantum signal.

    LOW POWER SYSTEM ON CHIP
    48.
    发明申请
    LOW POWER SYSTEM ON CHIP 有权

    公开(公告)号：US20220413544A1

    公开(公告)日：2022-12-29

    申请号：US17847636

    申请日：2022-06-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kyuseung HAN ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Kwang IL OH ,  Jae-Jin LEE

    IPC: G06F1/10 ,  G06F15/78

    Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.

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