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公开(公告)号：US09513918B2
公开(公告)日：2016-12-06
申请号：US13995974
申请日：2011-12-22
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mostafa Hagog , Jesus Corbal , Bret L Toll , Mark J Charney , Tal Uliel , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mostafa Hagog , Jesus Corbal , Bret L Toll , Mark J Charney , Tal Uliel , Zeev Sperber , Amit Gradstein
CPC分类号： G06F9/30196 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3867
摘要： An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from a first source operand and a second source operand based on index values stored in destination operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the first source operand and the second source operand may be copied to any one of the data element positions within the destination operand; and if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.
摘要翻译： 描述了用掩模来置换数据元素的装置和方法。 例如，根据一个实施例的方法包括以下操作：从掩模数据结构读取值以确定是否对目的地操作数的每个数据元素实施掩蔽; 如果对于特定数据元素没有被实现掩蔽，则基于存储在目的地操作数中的索引值从第一源操作数和第二源操作数中选择数据元素以被复制到目的地操作数中的数据元素位置，其中数据中的任何一个 可以将来自第一源操作数和第二源操作数的元素复制到目的地操作数中的任何一个数据元素位置; 并且如果针对目的地操作数的特定数据元素实现掩蔽，则对该特定数据元素执行指定的掩蔽操作。
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42.发明授权Instruction execution that broadcasts and masks data values at different levels of granularity 有权指令执行，以不同的粒度级别广播和屏蔽数据值公开(公告)号：US09424327B2
公开(公告)日：2016-08-23
申请号：US13976433
申请日：2011-12-23
CPC分类号： G06F21/6227 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/3802 , G06F17/30575 , G06F21/6254 , G06F21/70
摘要： An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication data structure at a second granularity. The second granularity is twice as fine as the first granularity.
摘要翻译： 描述了包括执行第一指令和第二指令的执行单元的装置。 执行单元包括输入寄存器空间，以在执行第一指令时存储待复制的第一数据结构，并且在执行第二指令时存储要复制的第二数据结构。 第一和第二数据结构都是打包数据结构。 第一打包数据结构的数据值是第二打包数据结构的数据值的两倍。 当执行第一指令以创建第一复制数据结构时，执行单元还包括复制第一数据结构的复制逻辑电路，以及在执行第二数据指令以创建第二复制数据结构时复制第二数据结构。 执行单元还包括掩蔽逻辑电路，以第一粒度掩蔽第一复制数据结构，并以第二粒度掩蔽第二复制数据结构。 第二粒度是第一粒度的两倍。
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43.发明授权Instruction execution unit that broadcasts data values at different levels of granularity 有权指令执行单元，以不同的粒度级别广播数据值公开(公告)号：US09336000B2
公开(公告)日：2016-05-10
申请号：US13976003
申请日：2011-12-23
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3887
摘要： An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The first data structure is four times as large as the second data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second instruction to create a second replication data structure.
摘要翻译： 描述了包括执行第一指令和第二指令的执行单元的装置。 执行单元包括输入寄存器空间，用于在执行第一指令时存储要复制的第一数据结构，并且在执行第二指令时存储要复制的第二数据结构。 第一和第二数据结构都是打包数据结构。 第一打包数据结构的数据值是第二打包数据结构的数据值的两倍。 第一个数据结构是第二个数据结构的四倍。 执行单元还包括复制逻辑电路，以在执行第一指令以创建第一复制数据结构时复制第一数据结构，并且在执行第二指令以创建第二复制数据结构时复制第二数据结构。
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公开(公告)号：US20150026439A1
公开(公告)日：2015-01-22
申请号：US13995974
申请日：2011-12-22
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mostafa Hagog , Jesus Corbal , Bret L. Toll , Mark J. Charney , Tal Uliel , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mostafa Hagog , Jesus Corbal , Bret L. Toll , Mark J. Charney , Tal Uliel , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30196 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3867
摘要： An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from a first source operand and a second source operand based on index values stored in destination operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the first source operand and the second source operand may be copied to any one of the data element positions within the destination operand; and if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.
摘要翻译： 描述了用掩模来置换数据元素的装置和方法。 例如，根据一个实施例的方法包括以下操作：从掩模数据结构读取值以确定是否对目的地操作数的每个数据元素实施掩蔽; 如果对于特定数据元素没有被实现掩蔽，则基于存储在目的地操作数中的索引值从第一源操作数和第二源操作数中选择数据元素以被复制到目的地操作数中的数据元素位置，其中数据中的任何一个 可以将来自第一源操作数和第二源操作数的元素复制到目的地操作数中的任何一个数据元素位置; 并且如果针对目的地操作数的特定数据元素实现掩蔽，则对该特定数据元素执行指定的掩蔽操作。
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45.发明申请公开(公告)号：US20140365747A1
公开(公告)日：2014-12-11
申请号：US13977612
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Moustapha Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Boris Ginzburg , Ziv Aviv
发明人： Elmoustapha Ould-Ahmed-Vall , Moustapha Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Boris Ginzburg , Ziv Aviv
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30101
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例，响应于包括目的地向量寄存器操作数，源向量寄存器操作数和操作码的单向量压缩水平和指令，执行压缩数据元素的水平部分和 被描述。
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46.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING CONVERSION OF A MASK REGISTER INTO A VECTOR REGISTER. 审中-公开用于将掩码寄存器转换为矢量寄存器的系统，设备和方法。公开(公告)号：US20140223138A1
公开(公告)日：2014-08-07
申请号：US13992235
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Amit Gradstein , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Amit Gradstein , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a mask register into a vector register in response to a single vector packed convert a mask register to a vector register instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法，用于响应于单向量压缩将掩码寄存器转换为向量寄存器，将掩码寄存器转换为向量寄存器指令，所述向量寄存器指令包括目的地向量寄存器操作数，源写入掩码 寄存器操作数和操作码。
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47.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING AN ABSOLUTE DIFFERENCE CALCULATION BETWEEN CORRESPONDING PACKED DATA ELEMENTS OF TWO VECTOR REGISTERS 审中-公开用于执行两个矢量寄存器的包装数据元素之间的绝对差分计算的系统，设备和方法公开(公告)号：US20140082333A1
公开(公告)日：2014-03-20
申请号：US13996849
申请日：2011-12-22
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F17/10
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor absolute difference calculation in response to a single vector packed absolute difference instruction that includes a first and second source vector register operand, a destination vector register operand, and an opcode are described.
摘要翻译： 描述了响应于包括第一和第二源向量寄存器操作数，目的向量寄存器操作数和操作码的单向量压缩绝对差指令在计算机处理器中执行绝对差计算的系统，装置和方法的实施例。
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48.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR EXTRACTING A WRITEMASK FROM A REGISTER 审中-公开从寄存器提取写入的系统，设备和方法公开(公告)号：US20140068227A1
公开(公告)日：2014-03-06
申请号：US13993519
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30007 , G06F9/30018 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30167 , G06F9/30185
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor mask extraction from a general purpose register in response to a single mask extraction from a general purpose register instruction that includes a source general purpose register operand, a destination writemask register operand, an immediate value, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于通用目的寄存器指令的单个掩码提取而从通用寄存器屏蔽提取，该通用寄存器指令包括源通用寄存器操作数，目的地写入寄存器操作数， 描述即时值和操作码。
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49.发明申请INSTRUCTION EXECUTION THAT BROADCASTS AND MASKS DATA VALUES AT DIFFERENT LEVELS OF GRANULARITY 有权在不同级别的格式下进行广播和屏蔽数据值的指令执行公开(公告)号：US20130290254A1
公开(公告)日：2013-10-31
申请号：US13976433
申请日：2011-12-23
IPC分类号： G06F17/30
CPC分类号： G06F21/6227 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/3802 , G06F17/30575 , G06F21/6254 , G06F21/70
摘要： An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure. The execution unit also includes masking logic circuitry to mask the first replication data structure at a first granularity and mask the second replication data structure at a second granularity. The second granularity is twice as fine as the first granularity.
摘要翻译： 描述了包括执行第一指令和第二指令的执行单元的装置。 执行单元包括输入寄存器空间，用于在执行第一指令时存储要复制的第一数据结构，并且在执行第二指令时存储要复制的第二数据结构。 第一和第二数据结构都是打包数据结构。 第一打包数据结构的数据值是第二打包数据结构的数据值的两倍。 当执行第一指令以创建第一复制数据结构时，执行单元还包括复制第一数据结构的复制逻辑电路，以及在执行第二数据指令以创建第二复制数据结构时复制第二数据结构。 执行单元还包括掩蔽逻辑电路，以第一粒度掩蔽第一复制数据结构，并以第二粒度掩蔽第二复制数据结构。 第二粒度是第一粒度的两倍。
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公开(公告)号：US20120185670A1
公开(公告)日：2012-07-19
申请号：US13007050
申请日：2011-01-14
CPC分类号： G06F9/30036 , G06F9/3012 , G06F9/3016 , G06F9/30185
摘要： A processing core implemented on a semiconductor chip is described. The processing core includes logic circuitry to identify whether vector instructions and integer scalar instructions are to be executed with two registers or three registers, where, in the case of two registers input operand information is destroyed in one of two registers, and, in the case of three registers input operand is not destroyed. The processing core also includes steering circuitry coupled to the logic circuitry. The steering circuitry is to control first data paths between scalar integer execution units and a scalar integer register bank such that two registers are accessed from the scalar register bank if two register execution is identified for the scalar integer instructions or three registers are accessed from the scalar integer register bank if three register execution is identified for the scalar integer instructions. The steering circuitry is also to control second data paths between vector execution units and a vector register bank such that two registers are accessed from the vector register bank if two register execution is identified for the vector instructions or three registers are accessed from the vector register bank if three register execution is identified for the vector instructions.
摘要翻译： 描述了在半导体芯片上实现的处理核心。 处理核心包括用于识别矢量指令和整数标量指令是否要用两个寄存器或三个寄存器执行的逻辑电路，其中在两个寄存器的情况下输入操作数信息在两个寄存器之一中被销毁，并且在这种情况下 的三个寄存器输入操作数不会被破坏。 处理核心还包括耦合到逻辑电路的转向电路。 转向电路是控制标量整数执行单元和标量整数寄存器组之间的第一数据路径，以便如果为标量整数指令识别两个寄存器执行，则从标量寄存器组访问两个寄存器，或者从标量访问三个寄存器 整数寄存器组如果为标量整数指令标识了三个寄存器执行。 转向电路还用于控制向量执行单元和向量寄存器组之间的第二数据路径，使得如果为向量指令识别了两个寄存器执行，则从向量寄存器组访问两个寄存器，或者从向量寄存器组访问三个寄存器 如果为向量指令识别了三个寄存器执行。
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