公开(公告)号：US20060056231A1

公开(公告)日：2006-03-16

申请号：US11225848

申请日：2005-09-12

Applicant: Philippe Roche ,  Francois Jacquet

Inventor： Philippe Roche ,  Francois Jacquet

IPC: G11C11/00

CPC classification number: H03K3/35625 ,  H03K3/013 ,  H03K3/0375 ,  H03K3/356156

Abstract: A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed between the first and second latch cells, each latch cell comprising a set of redundant data storage nodes. The transfer ports each include circuitry for writing data separately into each storage node.

Abstract translation: 多谐振荡器电路包括第一数据传输端口，其接收多谐振荡器输入数据作为输入，连接在第一传送端口的输出侧上的第一，主，锁存单元，第二从机，锁存单元和第二数据传输 端口位于第一和第二锁存单元之间，每个锁存单元包括一组冗余数据存储节点。 传送端口各自包括用于将数据分别写入每个存储节点的电路。

公开(公告)号：US20060056220A1

公开(公告)日：2006-03-16

申请号：US11225876

申请日：2005-09-12

Applicant: Philippe Roche ,  Francois Jacquet

Inventor： Philippe Roche ,  Francois Jacquet

IPC: G11C5/06

CPC classification number: G11C11/4125 ,  G11C5/005

Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

公开(公告)号：US20050285650A1

公开(公告)日：2005-12-29

申请号：US11159818

申请日：2005-06-23

Applicant: Sylvain Clerc ,  Philippe Roche ,  Francois Jacquet

Inventor： Sylvain Clerc ,  Philippe Roche ,  Francois Jacquet

IPC: G11C11/412 ,  H03K3/037 ,  H03K3/356 ,  H03K19/094

CPC classification number: H03K3/0375

Abstract: A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.

Abstract translation: 双稳态电路包括具有耦合到第一反相器的输出的一个输入的第一反相器和电容反相电路。 电容反相电路包括并联到输入端的电容反相电路和电容性反相电路的输出的第二反相器和电容电路。 双稳态电路还包括开关，当开关接收到有效验证信号时或者如果不是将电容性反转电路的输出耦合到第一反相器的输入端，则将电容反转电路的输出与第一反相器的输入隔离 第一台逆变器