公开(公告)号：US10277833B2

公开(公告)日：2019-04-30

申请号：US15479159

申请日：2017-04-04

Applicant: Google LLC

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

IPC: G09G5/36 ,  H04N5/262 ,  G06T1/60 ,  G06T1/20

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

公开(公告)号：US10216487B2

公开(公告)日：2019-02-26

申请号：US15591984

申请日：2017-05-10

Applicant: Google LLC

Inventor： Albert Meixner ,  Ofer Shacham ,  David Patterson ,  Daniel Frederic Finchelstein ,  Qiuling Zhu ,  Jason Rupert Redgrave

IPC: G06F8/10 ,  G06F8/20 ,  G06F9/30 ,  G06T1/20 ,  G06F17/50

Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

公开(公告)号：US10095479B2

公开(公告)日：2018-10-09

申请号：US14694890

申请日：2015-04-23

Applicant: Google LLC

Inventor： Albert Meixner ,  Ofer Shacham ,  David Patterson ,  Daniel Frederic Finchelstein ,  Qiuling Zhu ,  Jason Rupert Redgrave

IPC: G06F8/20 ,  G06F8/10 ,  G06T1/20 ,  G06F9/30

Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

公开(公告)号：US09986187B2

公开(公告)日：2018-05-29

申请号：US15628527

申请日：2017-06-20

Applicant: GOOGLE LLC

Inventor： Albert Meixner ,  Daniel Frederic Finchelstein ,  David Patterson ,  William R. Mark ,  Jason Rupert Redgrave ,  Ofer Shacham

IPC: G06F5/01 ,  G06F17/16 ,  G06F12/02 ,  G06T1/20 ,  H04N5/341 ,  H04N5/374

CPC classification number: H04N5/3742 ,  G06F5/015 ,  G06F12/0207 ,  G06F17/16 ,  G06T1/20 ,  H04N5/341

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.