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公开(公告)号：US10216720B2
公开(公告)日：2019-02-26
申请号：US15336907
申请日：2016-10-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
IPC: G06F17/27
Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.
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公开(公告)号：US10026477B2
公开(公告)日：2018-07-17
申请号：US15329845
申请日：2015-01-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jianhua Yang , Ning Ge , John Paul Strachan , Gary Gibson , Warren Jackson
Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.
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公开(公告)号：US10008264B2
公开(公告)日：2018-06-26
申请号：US15521542
申请日：2014-10-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ning Ge , Jianhua Yang , John Paul Strachan , Miao Hu
CPC classification number: G11C13/0069 , G06F17/11 , G06F17/16 , G06G7/16 , G11C7/1006 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/77
Abstract: A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.
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公开(公告)号：US20180114569A1
公开(公告)日：2018-04-26
申请号：US15570951
申请日：2016-03-11
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Brent Buchanan , Le Zheng
CPC classification number: G11C11/54 , G06F9/06 , G06N3/0454 , G06N3/0635 , G11C7/1006 , G11C7/1012 , G11C13/0007 , G11C13/0069
Abstract: Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.
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公开(公告)号：US20180095722A1
公开(公告)日：2018-04-05
申请号：US15282021
申请日：2016-09-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
CPC classification number: G06F7/523 , G06F7/5443 , G06F2207/4802 , G06F2207/4828 , G11C13/0007 , G11C13/0028 , G11C13/004
Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.
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Patent Agency Ranking
公开(公告)号：US20170316828A1
公开(公告)日：2017-11-02
申请号：US15522364
申请日：2014-10-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Miao Hu , Jianhua Yang , John Paul Strachan , Ning Ge
CPC classification number: G11C13/0069 , G06F17/16 , G06G7/16 , G11C13/0026 , G11C13/004 , G11C2213/77
Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.
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公开(公告)号：US09785615B1
公开(公告)日：2017-10-10
申请号：US15191669
申请日：2016-06-24
Applicant: Hewlett Packard Enterprise Development LP
CPC classification number: G06F17/16 , G11C7/1006 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2213/77
Abstract: Memristive computation of a cross product is disclosed. One example is a crossbar array of memory elements that include a number of column lines perpendicular to a number of row lines, a memory element located at each intersection of a row line and a column line. A programming voltage is applied at each memory element to change a resistance value to represent a respective entry in a skew symmetric matrix representing a first vector, and an input voltage is applied along each row line to represent a dimensional component of a second vector. Sensors located at each column line measure output voltages along column lines, where the output voltages are generated by applying input voltages received by memory elements located along the row line to resistance values of the respective memory elements. Differential amplifiers collate the output voltages for pairs of sensors to generate dimensional components of the cross product.
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公开(公告)号：US20250095736A1
公开(公告)日：2025-03-20
申请号：US18469457
申请日：2023-09-18
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , Catherine Graves , John Paul Strachan
IPC: G11C15/04
Abstract: A technique for compressing an analog content addressable memory (CAM) array is provided. Random input data is applied to the analog CAM array, and an average measure of similarity is calculated for each output row of the analog CAM array. Rows of the analog CAM array that have measures of similarity that are close to each other can be eliminated, such as by removing similar rows or merging together similar rows. Thus, the analog CAM array size can be reduced without a loss in accuracy of a model stored on the analog CAM array.
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公开(公告)号：US12205659B2
公开(公告)日：2025-01-21
申请号：US18483448
申请日：2023-10-09
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , John Paul Strachan , Catherine Graves
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.
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公开(公告)号：US20240047002A1
公开(公告)日：2024-02-08
申请号：US18483448
申请日：2023-10-09
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Giacomo Pedretti , John Paul Strachan , Catherine Graves
CPC classification number: G11C27/005 , G11C15/046
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.
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