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公开(公告)号：US20180108410A1
公开(公告)日：2018-04-19
申请号：US15566867
申请日：2015-05-29
IPC分类号： G11C13/00
CPC分类号： G11C13/0064 , G11C11/56 , G11C13/0069 , G11C2013/005 , G11C2013/0066 , G11C2013/0073 , G11C2013/0076 , G11C2013/009 , G11C2013/0092
摘要： An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.
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公开(公告)号：US20180025790A1
公开(公告)日：2018-01-25
申请号：US15216589
申请日：2016-07-21
CPC分类号： G11C29/789 , G11C13/0021 , H01L45/04 , H01L45/16
摘要： Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.
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公开(公告)号：US09785615B1
公开(公告)日：2017-10-10
申请号：US15191669
申请日：2016-06-24
CPC分类号： G06F17/16 , G11C7/1006 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2213/77
摘要： Memristive computation of a cross product is disclosed. One example is a crossbar array of memory elements that include a number of column lines perpendicular to a number of row lines, a memory element located at each intersection of a row line and a column line. A programming voltage is applied at each memory element to change a resistance value to represent a respective entry in a skew symmetric matrix representing a first vector, and an input voltage is applied along each row line to represent a dimensional component of a second vector. Sensors located at each column line measure output voltages along column lines, where the output voltages are generated by applying input voltages received by memory elements located along the row line to resistance values of the respective memory elements. Differential amplifiers collate the output voltages for pairs of sensors to generate dimensional components of the cross product.
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公开(公告)号：US11158370B2
公开(公告)日：2021-10-26
申请号：US16065364
申请日：2016-01-26
摘要： In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.
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公开(公告)号：US10157668B2
公开(公告)日：2018-12-18
申请号：US15566867
申请日：2015-05-29
摘要： An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.
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公开(公告)号：US20210193222A1
公开(公告)日：2021-06-24
申请号：US16065364
申请日：2016-01-26
IPC分类号： G11C13/00
摘要： In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.
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公开(公告)号：US09805770B1
公开(公告)日：2017-10-31
申请号：US15217739
申请日：2016-07-22
IPC分类号： G11C7/00 , G11C13/00 , G11C11/56 , H01L23/528
CPC分类号： G11C7/00 , G11C11/5614 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0066 , G11C2013/0071 , G11C2013/0076 , G11C2013/0083 , G11C2213/79 , H01L23/528
摘要： A set procedure of a one transistor, one memristor memory elements may comprise determining a gate voltage for the transistor based on the desired target value. Increasing set pulses may be applied to memristor while the gate is held at the determined gate voltage.
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公开(公告)号：US09691479B1
公开(公告)日：2017-06-27
申请号：US15142995
申请日：2016-04-29
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0076 , G11C2013/0088 , G11C2013/0092 , G11C2213/71 , G11C2213/74 , G11C2213/79
摘要： A method of operating a plurality of memristive cells coupled as a memristor array includes initializing a first select line, and, in parallel for a number of memristor cells in the first select line, determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance, and, in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line.
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