Process flow for sacrificial collar scheme with vertical nitride mask
    41.
    发明授权
    Process flow for sacrificial collar scheme with vertical nitride mask 有权
    具有垂直氮化物掩模的牺牲环方案的工艺流程

    公开(公告)号:US06534376B2

    公开(公告)日:2003-03-18

    申请号:US09930690

    申请日:2001-08-15

    申请人: Helmut Horst Tews

    发明人: Helmut Horst Tews

    IPC分类号: H01L2120

    CPC分类号: H01L27/1087

    摘要: A process flow for forming a sacrificial collar (132) within a deep trench (113) of a semiconductor memory cell. A nitride liner layer (120) is deposited over a substrate (111). A thin polysilicon layer (122) is deposited over the nitride liner layer (120), and an oxide layer (124) is formed. A resist (116) is deposited within the trenches (113) and etched back. The top portion of the oxide layer (124) is removed, and the resist (116) is removed from the trenches (113). The wafer (100) is exposed to a nitridation process to form a nitride layer (128) over exposed portions of the polysilicon layer (122). The oxide layer (124) and polysilicon layer (124) are removed from the bottom of the trenches. (113). The nitride liner layer (120) is removed from the bottom of the trenches (113). The polysilicon layer (122) is removed from the top of the trenches (113) to leave a sacrificial collar (132) in the top of the trenches 113 formed by nitride liner layer (120).

    摘要翻译: 一种用于在半导体存储单元的深沟槽(113)内形成牺牲套环(132)的工艺流程。 在衬底(111)上沉积氮化物衬垫层(120)。 在氮化物衬垫层(120)上沉积薄多晶硅层(122),并形成氧化物层(124)。 抗蚀剂(116)沉积在沟槽(113)内并被回蚀刻。 去除氧化物层(124)的顶部,并且从沟槽(113)去除抗蚀剂(116)。 将晶片(100)暴露于氮化工艺以在多晶硅层(122)的暴露部分上形成氮化物层(128)。 从沟槽的底部去除氧化物层(124)和多晶硅层(124)。 (113)。 从沟槽(113)的底部去除氮化物衬垫层(120)。 从沟槽(113)的顶部去除多晶硅层(122),以在由氮化物衬垫层(120)形成的沟槽113的顶部留下牺牲环(132)。

    Combined preanneal/oxidation step using rapid thermal processing
    42.
    发明授权
    Combined preanneal/oxidation step using rapid thermal processing 有权
    使用快速热处理的组合式预退火/氧化步骤

    公开(公告)号:US06436846B1

    公开(公告)日:2002-08-20

    申请号:US09146870

    申请日:1998-09-03

    IPC分类号: H01L21469

    摘要: A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.

    摘要翻译: 一种组合的预退火/氧化步骤,其使用快速热处理(RTP)来处理硅晶片以形成给定厚度的热氧化物,同时调节裸露区深度和体微观缺陷密度(BMD),包括:将晶片暴露于 在环境压力下的氧化环境中的受控温度和受控的预退火时间,以获得预先选定以对应于预选的剥离区深度的目标热氧化物厚度。