公开(公告)号：US06436846B1

公开(公告)日：2002-08-20

申请号：US09146870

申请日：1998-09-03

申请人： Helmut Horst Tews ,  Martin Schrems ,  Thomas Gaertner

发明人： Helmut Horst Tews ,  Martin Schrems ,  Thomas Gaertner

IPC分类号： H01L21469

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662

摘要： A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.

摘要翻译： 一种组合的预退火/氧化步骤，其使用快速热处理（RTP）来处理硅晶片以形成给定厚度的热氧化物，同时调节裸露区深度和体微观缺陷密度（BMD），包括：将晶片暴露于 在环境压力下的氧化环境中的受控温度和受控的预退火时间，以获得预先选定以对应于预选的剥离区深度的目标热氧化物厚度。

公开(公告)号：US06537926B1

公开(公告)日：2003-03-25

申请号：US09638309

申请日：2000-08-14

申请人： Martin Schrems ,  Helmut Horst Tews

发明人： Martin Schrems ,  Helmut Horst Tews

IPC分类号： H01L2131

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662

摘要： A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.g., in oxygen and/or water vapor, at the high oxidizing temperature to increase uniformly the oxide layer to a selective final thickness, e.g., of 20-100 angstroms, whereupon the resultant uniform final thickness oxide layer-containing wafer is recovered from the furnace.

摘要翻译： 提供了两步逐步热氧化工艺以改善半导体晶片制造中薄氧化物层的厚度均匀性。 诸如硅的半导体晶片，具有在其上形成氧化物层但基本上不含氧化物层的表面，例如在室温下被加载到维持在低负载温度的氧化炉中，例如 ，400-600℃，并且将晶片温度调节至低氧化温度，例如400-600℃，同时晶片处于惰性，例如氮气氛下。 然后将晶片在低氧化温度下进行初始氧化，例如在干燥的氧气中，以在表面上形成均匀的初始厚度氧化物，例如二氧化硅，例如至多10埃的层，之后 炉温升高到高的氧化温度，例如700-1200℃，同时晶片处于惰性气氛。 接着在高氧化温度下将晶片进行最终氧化，例如在氧气和/或水蒸气中，以将氧化物层均匀地增加至选择性最终厚度，例如20-100埃，由此得到均匀的最终厚度 从炉中回收含氧化物层的晶片。

公开(公告)号：US06235651B1

公开(公告)日：2001-05-22

申请号：US09395952

申请日：1999-09-14

申请人： Martin Schrems ,  Helmut Horst Tews

发明人： Martin Schrems ,  Helmut Horst Tews

IPC分类号： H01L2131

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662

摘要： A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.g., in oxygen and/or water vapor, at the high oxidizing temperature to increase uniformly the oxide layer to a selective final thickness, e.g., of 20-100 angstroms, whereupon the resultant uniform final thickness oxide layer-containing wafer is recovered from the furnace.

摘要翻译： 提供了两步逐步热氧化工艺以改善半导体晶片制造中薄氧化物层的厚度均匀性。 诸如硅的半导体晶片，具有在其上形成氧化物层但基本上不含氧化物层的表面，例如在室温下被加载到维持在低负载温度的氧化炉中，例如 ，400-600℃，并且将晶片温度调节至低氧化温度，例如400-600℃，同时晶片处于惰性，例如氮气氛下。 然后将晶片在低氧化温度下进行初始氧化，例如在干燥的氧气中，以在表面上形成均匀的初始厚度氧化物，例如二氧化硅，例如至多10埃的层，之后 炉温升高到高的氧化温度，例如700-1200℃，同时晶片处于惰性气氛。 接着在高氧化温度下将晶片进行最终氧化，例如在氧气和/或水蒸气中，以将氧化物层均匀地增加至选择性最终厚度，例如20-100埃，由此得到均匀的最终厚度 从炉中回收含氧化物层的晶片。

公开(公告)号：US20110278680A1

公开(公告)日：2011-11-17

申请号：US13193692

申请日：2011-07-29

申请人： Helmut Horst Tews ,  Andre Schenk

发明人： Helmut Horst Tews ,  Andre Schenk

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.

摘要翻译： 在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。 栅电极与半导体本体电绝缘。 沿着栅电极的侧壁形成第一侧壁间隔物。 邻近第一侧壁间隔件形成牺牲侧壁间隔物。 牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。 平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。 然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。 所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。 然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

公开(公告)号：US20100330771A1

公开(公告)日：2010-12-30

申请号：US12876866

申请日：2010-09-07

申请人： Hans-Joachim Barth ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Helmut Horst Tews

IPC分类号： H01L21/02

CPC分类号： H01L28/75 ,  G06F17/5068 ,  H01L21/76897 ,  H01L22/14 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/562 ,  H01L23/585 ,  H01L27/0611 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.

摘要翻译： 公开了在半导体部件上形成防潮电容器的结构和方法。 电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

公开(公告)号：US07157328B2

公开(公告)日：2007-01-02

申请号：US11047312

申请日：2005-01-31

申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

IPC分类号： H01L21/8242

CPC分类号： H01L21/30604 ,  H01L29/66181

摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

公开(公告)号：US06967147B1

公开(公告)日：2005-11-22

申请号：US09714356

申请日：2000-11-16

申请人： Helmut Horst Tews ,  Jochen Beintner

发明人： Helmut Horst Tews ,  Jochen Beintner

IPC分类号： H01L20060101 ,  H01L21/265 ,  H01L21/28 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06

CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/10873 ,  Y10S438/981

摘要： Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.

摘要翻译： 用于通过使用氮注入并入不同厚度的栅极氧化物来形成用于DRAMS的双栅极氧化物的工艺。 使用倾斜的氮气注入或氮化物间隔物来产生“阴影效应”或区域，这限制了接近有效区域边缘的氮剂量。 氮剂量的减少导致在与浅沟槽相邻的有源区（AA）处的栅极氧化物厚度增加，增加了寄生角装置的阈值并且减小了副Vt（阈值电压）和结漏电。

公开(公告)号：US06677197B2

公开(公告)日：2004-01-13

申请号：US10032040

申请日：2001-12-31

申请人： Stephan Kudelka ,  Helmut Horst Tews

发明人： Stephan Kudelka ,  Helmut Horst Tews

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L29/66181

摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.

摘要翻译： 在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a） 在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模 衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物 在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物 进行多化学机械抛光。

公开(公告)号：US08569820B2

公开(公告)日：2013-10-29

申请号：US13344714

申请日：2012-01-06

申请人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

IPC分类号： H01L27/108

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

公开(公告)号：US07767562B2

公开(公告)日：2010-08-03

申请号：US11235330

申请日：2005-09-26

申请人： Helmut Horst Tews ,  Jochen Beintner

发明人： Helmut Horst Tews ,  Jochen Beintner

IPC分类号： H01L21/425

CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/10873 ,  Y10S438/981

摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.

摘要翻译： 半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。 第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。 以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。 以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。