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公开(公告)号：US20230244450A1
公开(公告)日：2023-08-03
申请号：US18104550
申请日：2023-02-01
Applicant: Infineon Technologies AG
Inventor： Rainer Göettfert , Gerd Dirscherl , Berndt Gammel
Abstract: According to one exemplary embodiment, an integrated circuit is described, comprising multiple noise sources, each noise source being configured to output a respective set of noise bits for a random vector, a combinational logic circuit configured to process a noise bit vector, corresponding to a concatenation of the bits of the sets of noise bits, in accordance with a multiplication by a matrix to produce a processed noise bit vector, with the result that the processed noise bit vector comprises more bits than each of the sets of noise bits and comprises fewer bits than the noise bit vector; and a post-processing logic circuit configured to generate the random vector from the processed noise bit vector.
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公开(公告)号：US10992464B2
公开(公告)日：2021-04-27
申请号：US16242003
申请日：2019-01-08
Applicant: Infineon Technologies AG
Inventor： Berndt Gammel , Bernd Meyer
Abstract: A chip includes a processing device to perform cryptographic operations by secret data; a memory to store a first plurality of information portions that correspond to a first breakdown of the data and from which the secret data are reconstructible by combination of the first plurality of information portions; a random number generator to provide random values; and a conversion device to ascertain second breakdowns of the data into a second plurality of information portions, from which the secret data are reconstructible and to control the memory for an ascertained second breakdown to store the present second plurality of information portions. The conversion device is further configured to ascertain the second breakdowns based on the random values and/or to determine the interval of time between the ascertaining and storing of a second breakdown and the ascertaining and storing of the subsequent second breakdown based on the random values.
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公开(公告)号：US10607033B2
公开(公告)日：2020-03-31
申请号：US15883120
申请日：2018-01-30
Applicant: Infineon Technologies AG
Inventor： Thomas Kuenemund , Berndt Gammel
IPC: G06F21/75 , G06F21/73 , G06F21/72 , H04L9/32 , G11C7/10 , G11C7/24 , H04L9/08 , G09C1/00 , G11C11/412 , G11C11/419 , H03K19/003
Abstract: According to one embodiment, a physical uncloneable function circuit for providing a protected output bit is described including at least one physical uncloneable function circuit element configured to output a bit of a physical uncloneable function value, a physical uncloneable function bit output terminal and a coupling circuit connected between the physical uncloneable function circuit element and the physical uncloneable function bit output terminal configured to receive a control signal, supply the bit to the physical uncloneable function bit output terminal for a first state of the control signal and supply the complement of the bit to the physical uncloneable function bit output terminal for a second state of the control signal.
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公开(公告)号：US20200074076A1
公开(公告)日：2020-03-05
申请号：US16678397
申请日：2019-11-08
Applicant: Infineon Technologies AG
Inventor： Berndt Gammel , Stefan Mangard , Steffen Sonnekalb
Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.
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公开(公告)号：US10418996B2
公开(公告)日：2019-09-17
申请号：US15718033
申请日：2017-09-28
Applicant: Infineon Technologies AG
Inventor： Thomas Kuenemund , Molka Ben Romdhane , Berndt Gammel
IPC: H03K19/007 , H03K3/3562
Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.
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Patent Agency Ranking
公开(公告)号：US09678924B2
公开(公告)日：2017-06-13
申请号：US14470953
申请日：2014-08-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Rainer Goettfert , Berndt Gammel , Thomas Kuenemund
CPC classification number: G06F17/16 , G06F7/588 , H04L9/0866 , H04L2209/34
Abstract: A method for reconstructing a first vector from a second vector includes: storing code for the row vectors according to a first code and a second code; correcting the row vectors of the second vector corresponding to the first vector so that the row vectors of the second vector have the same code as the row vectors of the first vector; calculating the code of the column vectors of the second vector according to the second code; comparing the code of the row vectors of the second vector with the code of the column vectors of the first vector; identifying the columns in which the first vector is unequal to the second vector; the rows in which the first vector is unequal to the second vector; and the components in which the first vector is not equal to the second vector, and correcting the components of the second vector.
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公开(公告)号：US20170110418A1
公开(公告)日：2017-04-20
申请号：US14887367
申请日：2015-10-20
Applicant: Infineon Technologies AG
Inventor： Thomas Kuenemund , Berndt Gammel
IPC: H01L23/00 , H01L27/118
CPC classification number: H01L23/576 , H01L27/11807 , H03K3/35625
Abstract: According to one embodiment, a method for manufacturing a digital circuit is described comprising forming a modified RS master latch with an output for outputting an output signal comprising forming two field effect transistors which are virtually identical wherein the two formed field effect transistors are connected to each other in an RS latch type configuration and the respective threshold voltages of the two field effect transistors are set to be different from each other so that the output signal of the modified RS master latch in response to an RS latch forbidden input transition has a predetermined defined logic state, forming an RS slave latch having a set input and a reset input and connecting the set input or the reset input of the RS-slave latch to the output of the modified RS master latch.
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公开(公告)号：US09509508B2
公开(公告)日：2016-11-29
申请号：US14074279
申请日：2013-11-07
Applicant: Infineon Technologies AG
Inventor： Berndt Gammel , Wieland Fischer , Stefan Mangard
CPC classification number: H04L9/0869 , H04L9/0637 , H04L9/0668 , H04L9/0866 , H04L9/3242
Abstract: A key-generating apparatus is provided for generating a session key which is known to a first communication apparatus and a second communication apparatus, for the first communication apparatus, from secret information which may be determined by the first and second communication apparatuses. The key-generating apparatus includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information, and a second module operable to use the session key for communication with the second communication apparatus.
Abstract translation: 提供了一种密钥生成装置，用于从可由第一和第二通信装置确定的秘密信息生成第一通信装置和第二通信装置已知的会话密钥。 密钥生成装置包括：第一模块，其可操作以使用随机数的至少一部分和所述秘密信息的一部分的级联来计算会话密钥;以及第二模块，其可操作以使用所述会话密钥与所述第二模块进行通信 通信设备。
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公开(公告)号：US09431353B2
公开(公告)日：2016-08-30
申请号：US14311378
申请日：2014-06-23
Applicant: Infineon Technologies AG
Inventor： Thomas Kuenemund , Berndt Gammel
IPC: H01L23/00 , H03K19/003 , H01L27/088 , H01L21/8234
CPC classification number: H01L23/576 , H01L21/823412 , H01L21/823418 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H03K3/356104 , H03K19/00315 , H03K19/094 , H01L2924/00
Abstract: A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input has a predetermined defined logic state.
Abstract translation: 描述了一种制造数字电路的方法，包括形成两个场效应晶体管，连接场效应晶体管，使得当场效应晶体管的阈值电压时，响应于预定输入的数字电路的输出信号具有未定义的逻辑状态 相等并且设置场效应晶体管中的至少一个的阈值电压，使得响应于预定输入的数字电路的输出信号具有预定的定义的逻辑状态。
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公开(公告)号：US20160210121A1
公开(公告)日：2016-07-21
申请号：US14994367
申请日：2016-01-13
Applicant: Infineon Technologies AG
Inventor： Berndt Gammel , Rainer Goettfert
Abstract: A device for generating a random number is suggested, the device comprising at least two shift registers, a transformation function that generates the random number based on at least one cell of each of the at least two shift registers.
Abstract translation: 提出了一种用于产生随机数的装置，该装置包括至少两个移位寄存器，基于至少两个移位寄存器中的每一个的至少一个单元产生随机数的变换函数。
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