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    Physically obfuscated circuit
    1.
    发明授权
    Physically obfuscated circuit 有权

    公开(公告)号：US11437330B2

    公开(公告)日：2022-09-06

    申请号：US17004036

    申请日：2020-08-27

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kuenemund

    IPC: H01L23/00 ,  H01L27/092

    Abstract: A physically obfuscated circuit (POC) circuit including a plurality of subcircuits, each comprising at least one p-channel field effect transistor (FET) and at least one n-channel FET, connected such that the at least one n-channel FET, if supplied with an upper supply potential at its gate, supplies a lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET.

    Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering
    3.
    发明授权
    Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering 有权
    半导体芯片具有交叉耦合晶体管的电路以阻止逆向工程

    公开(公告)号：US09431398B2

    公开(公告)日：2016-08-30

    申请号：US14262830

    申请日：2014-04-28

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kuenemund

    IPC: H01L23/528 ,  H01L27/092 ,  H01L23/00

    CPC classification number: H01L27/092 ,  H01L23/528 ,  H01L23/576 ,  H01L2924/0002 ,  H03K19/00315 ,  H03K19/0948 ,  H03K19/215 ,  H01L2924/00

    Abstract: According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip.

    Abstract translation: 根据一个实施例，芯片具有至少一个p沟道场效应晶体管（FET）的电路; 至少一个n沟道FET; 第一和第二电源端子; 其中所述n沟道FET（如果在其栅极处被提供上电源电位）将较低的电源电位提供给p沟道FET的栅极; 并且如果在其栅极处提供较低的电源电位，则p沟道FET将上电源电位提供给n沟道FET的栅极; 其中p沟道FET和n沟道FET的栅极的逻辑状态只能通过第一和第二电源电压中的至少一个改变到电路; 以及耦合到p沟道FET或n沟道FET的栅极的连接以及半导体芯片的另一个部件。

    CHIP AND METHOD FOR DETECTING AN ATTACK ON A CHIP
    5.
    发明申请
    CHIP AND METHOD FOR DETECTING AN ATTACK ON A CHIP 有权
    用于检测芯片上的攻击的芯片和方法

    公开(公告)号：US20150214163A1

    公开(公告)日：2015-07-30

    申请号：US14166930

    申请日：2014-01-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Thomas Kuenemund ,  Jan Otterstedt ,  Christoph Saas

    IPC: H01L23/00 ,  G01R31/28

    CPC classification number: H01L23/57 ,  G01R31/2884 ,  G06F21/87 ,  G06F21/88 ,  H01L22/34 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: According to one embodiment, a chip is described comprising a transistor level, a semiconductor region in, below, or in and below the transistor level, a test signal circuit configured to supply a test signal to the semiconductor region, a determiner configured to determine a behavior of the semiconductor region in response to the test signal and a detector configured to detect a change of geometry of the semiconductor region based on the behavior and a reference behavior of the semiconductor region in response to the test signal.

    Abstract translation: 根据一个实施例，描述了芯片，其包括晶体管电平，位于晶体管电平以下或之下的半导体区域，被配置为向半导体区域提供测试信号的测试信号电路，被配置为确定 响应于测试信号的半导体区域的行为以及被配置成基于测试信号的半导体区域的行为和参考行为来检测半导体区域的几何形状的变化的检测器。

    CIRCUIT
    6.
    发明申请
    CIRCUIT 有权
    电路

    公开(公告)号：US20140035624A1

    公开(公告)日：2014-02-06

    申请号：US13947156

    申请日：2013-07-22

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kuenemund

    IPC: H03K17/30

    CPC classification number: H03K17/30 ,  G11C7/20 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

    Abstract: In accordance with various embodiments, a circuit is provided, including an output node, a first potential varying stage, which is designed to couple the output node to a supply potential in reaction to an input signal, and a second potential varying stage, which is designed to couple the output node to the supply potential if the difference between the potential of the output node and the supply potential lies below a predefined threshold value.

    Abstract translation: 根据各种实施例，提供一种电路，包括输出节点，被设计成将输出节点耦合到与输入信号反应的电源电位的第一电位变化级和第二电位变化级，第二电位变化级是 如果输出节点的电位和电源电位之间的差异低于预定义的阈值，则将输出节点耦合到电源电位。

    Chip and method for manufacturing a chip
    7.
    发明授权
    Chip and method for manufacturing a chip 有权

    公开(公告)号：US11410987B2

    公开(公告)日：2022-08-09

    申请号：US17176196

    申请日：2021-02-16

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kuenemund

    IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40 ,  H01L27/118

    Abstract: A chip is described including a semiconductor layer including doped regions; a metallization layer on the semiconductor layer and at least one cell row including p-channel field effect transistors and n-channel field effect transistors, wherein the doped regions form source regions and drain regions of the p-channel field effect transistors and the n-channel field effect transistors; contacts extending from the source regions, the drain regions and gate regions of the p-channel field effect transistors and the n-channel field effect transistors to the metallization layer, wherein the metallization layer is structured in accordance with a metallization grid such that the p-channel field effect transistors and the n-channel field effect transistors are connected to form one or more logic gates.

    Master-slave D flip-flop
    8.
    发明授权
    Master-slave D flip-flop 有权

    公开(公告)号：US11239830B2

    公开(公告)日：2022-02-01

    申请号：US17198477

    申请日：2021-03-11

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kuenemund ,  Anton Huber

    IPC: H03K3/037 ,  H03K3/012 ,  H03K3/3562 ,  H03K3/356

    Abstract: A master-slave D flip-flop is disclosed having gates configured to supply two second intermediate signals as a function of first intermediate signals and a clock signal, and a slave circuit connected to a transfer circuit to form at least one output signal of the flip-flop from the second intermediate signals. The slave circuit is configured, when the second intermediate signals have, after a preceding pair of states, a predetermined pair of states, to maintain the at least one output signal as given by the preceding pair of states. The transfer circuit has a control input and is configured to generate the second intermediate signals to have the predetermined pair of states in response to a predetermined control signal state at the control input.

    Electronic transmission element
    10.
    发明授权
    Electronic transmission element 有权

    公开(公告)号：US09729133B2

    公开(公告)日：2017-08-08

    申请号：US14321843

    申请日：2014-07-02

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kuenemund

    IPC: H03K17/00 ,  H03K3/84

    CPC classification number: H03K17/002 ,  H03K3/84 ,  Y10T307/76

    Abstract: According to an embodiment, an electronic transmission element is provided that has a first input and a first output. The first input is coupled to the first output by means of two first, parallel-connected complementary switches. The first switches each have a control input. The electronic transmission element further has a second input and a second output. The second input is coupled to the second output by means of two second, parallel-connected complementary switches. The second switches each have a control input. The first output is coupled to the control inputs of the second switches and the second output is coupled to the control inputs of the first switches.

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