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    MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT
    4.
    发明申请
    MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20180151244A1

    公开(公告)日：2018-05-31

    申请号：US15821871

    申请日：2017-11-24

    Applicant: Infineon Technologies AG

    Inventor： Jan Otterstedt ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

    IPC: G11C29/02 ,  G11C7/06

    CPC classification number: G11C29/025 ,  G11C7/06 ,  G11C29/12005 ,  G11C29/702 ,  G11C29/82 ,  G11C2029/1202 ,  G11C2029/4402

    Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in a non-volatile memory cell array along a rows and columns, a plurality of word lines, each word line coupled with one or more memory cells, a plurality of non-volatile marking memory cells, wherein at least one word line of the plurality of word lines is associated with one or more marking memory cells, and a plurality of marking bit lines, each associated with marking memory cells, a plurality of marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

    DATA PROCESSING ARRANGEMENT AND METHOD FOR DATA PROCESSING
    9.
    发明申请
    DATA PROCESSING ARRANGEMENT AND METHOD FOR DATA PROCESSING 有权
    数据处理安排和数据处理方法

    公开(公告)号：US20150032992A1

    公开(公告)日：2015-01-29

    申请号：US14341925

    申请日：2014-07-28

    Applicant: Infineon Technologies AG

    Inventor： Rainer Goettfert ,  Berndt Gammel ,  Gerd Dirscherl

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3004 ,  G06F9/3885 ,  G06F21/85

    Abstract: A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.

    Abstract translation: 提供具有第一处理部件和第二处理部件的处理装置。 第一组件具有第一输出存储器和第二输出存储器以及使用存储要输出的值的第一存储器的控制装置，并且第二存储器存储根据该值的规定函数所基于的值。 每当第二组件读取存储在第一存储器中的值时，控制装置将新的值存储在第一存储器中。 第二组件具有读取存储在第一和第二存储器中的值的读取装置，以及检查从第二存储器读取的值是否根据从第一存储器读取的值的规定函数为基础的处理装置，并且依赖于 在结果上，处理从第一个内存读取的值。

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