公开(公告)号：US20190045461A1

公开(公告)日：2019-02-07

申请号：US16134400

申请日：2018-09-18

Applicant: Intel Corporation

Inventor： Juan Fang ,  Laurent Cariou ,  Shahrnaz Azizi ,  Alexander W. Min ,  Thomas J. Kenney ,  Rath Vannithamby ,  Ravikumar Balakrishnan

IPC: H04W52/36 ,  H04W72/04 ,  H04W52/24

CPC classification number: H04W52/367 ,  H04B17/318 ,  H04L61/6022 ,  H04W52/245 ,  H04W72/0473 ,  H04W74/006 ,  H04W74/0816 ,  H04W84/12 ,  H04W88/08

Abstract: Methods, apparatuses, and computer readable media for power reduction in a wireless network are disclosed. An apparatus of a first access point is disclosed comprising processing circuitry configure to decode a first PPDU, the first PPDU including a trigger for control (TOC) frame, the TOC frame comprising resource allocations for deferral transmissions, the TOC frame including a first duration field indicating a duration of a transmission opportunity (TXOP). The processing circuitry may be further configured to respond to a determination that the TOC frame includes a resource allocation by encoding a second PPDU including a preamble portion and a media access control (MAC) portion including a receive with condition (ARC) frame, the ARC frame including a second duration field indicating a remaining duration of the TXOP, an address field indicating a MAC address of the first AP, and a condition field indicating a condition.

公开(公告)号：US20180288706A1

公开(公告)日：2018-10-04

申请号：US15473082

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Juan Fang ,  Shahrnaz Azizi ,  Minyoung Park

IPC: H04W52/02 ,  H04L27/26 ,  H04W28/06

Abstract: A wireless communication system, system and method. A wireless communication device comprises a memory, and processing circuitry including logic. The processing circuitry is to decode a wake-up payload, when a main radio associated with the device is in a sleep state, using an operational cyclic prefix length for the packet. The operational cyclic prefix length may be one of a fixed cyclic prefix length, a cyclic prefix length used for a last packet transmission by the main radio, and a selected cyclic prefix length determined by the processing circuitry. The processing circuitry may further cause a wake-up of the main radio based on the wake-up payload to allow the main radio to process a subsequent packet after waking up.

公开(公告)号：US20180183905A1

公开(公告)日：2018-06-28

申请号：US15390623

申请日：2016-12-26

Applicant: Intel Corporation

Inventor： Shahrnaz Azizi ,  Juan Fang ,  Minyoung Park ,  Thomas J. Kenney

IPC: H04L29/06 ,  H04L5/00 ,  H04W40/00

CPC classification number: H04L5/0044 ,  H04L5/003 ,  H04L5/0046 ,  H04L5/0053 ,  H04L27/02 ,  H04L27/2601 ,  H04L27/2602 ,  H04L27/2613 ,  H04L27/2615 ,  H04W52/0203 ,  H04W52/0209 ,  H04W72/0453 ,  H04W84/12 ,  H04W84/22 ,  Y02D70/00 ,  Y02D70/10 ,  Y02D70/1226 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/14 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/20 ,  Y02D70/26

Abstract: A wireless communication device, system and method. The device comprises a memory and processing circuitry coupled to the memory. The processing circuitry has logic to multiplex a first signal into a second signal, and to encode the first signal and second signal using orthogonal frequency divisional multiple access (OFDMA), a the first signal being contained within one of a plurality of smallest resource units (smallest RUs) of the second signal, the first signal and the second signal having a same number of tones and a same tone spacing in a frequency domain, and a same symbol duration in a time domain, the first signal including a number of repeated portions in a time domain and a number of nulls in a frequency domain and representing an information bit of “1”; and cause transmission of a multiplexed signal including the second signal and the first signal multiplexed into the second signal.