公开(公告)号：US20220131706A1

公开(公告)日：2022-04-28

申请号：US17568919

申请日：2022-01-05

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

公开(公告)号：US20220109558A1

公开(公告)日：2022-04-07

申请号：US17551525

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Santosh Ghosh ,  Shalini Sharma ,  Eduard Lecha ,  Manoj Sastry ,  Xiaoyu Ruan ,  Sanu Mathew

IPC: H04L9/06

Abstract: In one example an apparatus comprises verification circuitry to store an object image in a computer readable memory external to an XMSS verifier circuitry and verify the object image by repeating operations to receive, in a local memory of the XMSS verifier circuitry, a fixed-sized block of data from the object image and process the fixed-sized block of data to compute the signature verification. Other examples may be described.

公开(公告)号：US11223483B2

公开(公告)日：2022-01-11

申请号：US16456064

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

公开(公告)号：US11121856B2

公开(公告)日：2021-09-14

申请号：US16010206

申请日：2018-06-15

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

IPC: H04L9/06 ,  G09C1/00 ,  G06F7/72

Abstract: Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.

公开(公告)号：US11082241B2

公开(公告)日：2021-08-03

申请号：US15941050

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Manoj Sachdev ,  Vikram Suresh ,  Sanu Mathew ,  Sudhir Satpathy

IPC: H04L9/32 ,  H04L9/08 ,  G06F9/30 ,  G06F21/44 ,  G09C1/00 ,  H03M7/30

Abstract: An embodiment of a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.

公开(公告)号：US10754619B2

公开(公告)日：2020-08-25

申请号：US16143770

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Sanu Mathew ,  Vikram Suresh ,  Raghavan Kumar

IPC: G06F7/58 ,  H04L9/32 ,  G06F21/75

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.

公开(公告)号：US20190199517A1

公开(公告)日：2019-06-27

申请号：US16288536

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

IPC: H04L9/06

CPC classification number: H04L9/0637 ,  H04L9/065

Abstract: An integrated circuit features technology for generating a keystream. The integrated circuit comprises a cipher block with a linear feedback shift register (LFSR) and a finite state machine (FSM). The LFSR and the FSM are configured to generate a stream of keys, based on an initialization value and an initialization key. The FSM comprises an Sbox that is configured to use a multiplicative mask to mask data that is processed by the Sbox when the LFSR and the FSM are generating the stream of keys. Other embodiments are described and claimed.

公开(公告)号：US09843441B2

公开(公告)日：2017-12-12

申请号：US14035508

申请日：2013-09-24

Applicant: Intel Corporation

Inventor： Sanu Mathew ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

IPC: H04L9/28 ,  H04L9/06

CPC classification number: H04L9/0631 ,  H04L2209/24

Abstract: Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.