公开(公告)号：US20220109558A1

公开(公告)日：2022-04-07

申请号：US17551525

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Santosh Ghosh ,  Shalini Sharma ,  Eduard Lecha ,  Manoj Sastry ,  Xiaoyu Ruan ,  Sanu Mathew

IPC: H04L9/06

Abstract: In one example an apparatus comprises verification circuitry to store an object image in a computer readable memory external to an XMSS verifier circuitry and verify the object image by repeating operations to receive, in a local memory of the XMSS verifier circuitry, a fixed-sized block of data from the object image and process the fixed-sized block of data to compute the signature verification. Other examples may be described.

公开(公告)号：US09395784B2

公开(公告)日：2016-07-19

申请号：US13870195

申请日：2013-04-25

Applicant: Intel Corporation

Inventor： Inder Sodhi ,  Sanjeev Jahagirdar ,  Ryan Wells ,  Zeev Offen ,  Shalini Sharma ,  Ken Drottar

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/32 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a core to execute instructions, an agent to perform an operation independently of the core, a fabric to couple the core and agent and including a plurality of domains and a logic to receive isochronous parameter information from the agent and environmental information of a platform and to generate first and second values, and a power controller to control a frequency of the domains based at least in part on the first and second values. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的核心，独立于核心执行操作的代理，耦合核心和代理的结构，并且包括多个域以及从代理接收等时参数信息的逻辑，以及 平台的环境信息并产生第一和第二值，以及功率控制器，至少部分地基于第一和第二值来控制域的频率。 描述和要求保护其他实施例。

公开(公告)号：US09280510B2

公开(公告)日：2016-03-08

申请号：US14600470

申请日：2015-01-20

Applicant: Intel Corporation

Inventor： Sridharan Ranganathan ,  David J. Harriman ,  Anoop Mukker ,  Satheesh Chellappan ,  Karthi R. Vadivelu ,  Shalini Sharma ,  Zeeshan Sarwar

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/4027 ,  G06F13/426 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract translation: 用于本文提供的设备中的单元之间的低功率，高带宽通信的接口。 接口包括USB 3.0系统接口和配置为便于USB 3.0系统接口和M-PHY接口之间的通信的SuperSpeed芯片间（SSIC）协议适配器。