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公开(公告)号:US11335841B2
公开(公告)日:2022-05-17
申请号:US17001703
申请日:2020-08-25
Applicant: Japan Display Inc.
Inventor: Yasuhiro Kanaya , Gen Koide
Abstract: An LED module includes a first metal layer disposed on a base surface and an LED chip disposed on the first metal layer. The first metal layer includes a first end portion forming a contour away from the base surface, and a curved portion between a region overlapping the LED chip and the first end portion.
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公开(公告)号:US11300835B2
公开(公告)日:2022-04-12
申请号:US16937962
申请日:2020-07-24
Applicant: Japan Display Inc.
Inventor: Takenori Hirota , Yasuhiro Kanaya , Hidehiro Sonoda , Toshiki Kaneko
IPC: G02F1/1339 , G02F1/1333
Abstract: A reliability of seal portion of a liquid crystal display device can be improved by the following structure. A liquid crystal display device includes: a TFT substrate which includes a display region and a terminal part, and has an inorganic insulating film formed on an organic passivation film and an alignment film formed over the inorganic insulating film; a counter substrate, the TFT substrate and the counter substrate bonded together by a sealing material formed at a seal part surrounding the display region; and a liquid crystal sealed inside. At the seal part, a transparent conductive oxide film is formed between the inorganic insulating film and the alignment film. The transparent conductive oxide film exists inside an edge of the TFT substrate and hence, the edge of the TFT substrate is free of the transparent conductive oxide film.
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公开(公告)号:US10761380B2
公开(公告)日:2020-09-01
申请号:US16373832
申请日:2019-04-03
Applicant: Japan Display Inc.
Inventor: Takenori Hirota , Yasuhiro Kanaya , Hidehiro Sonoda , Toshiki Kaneko
IPC: G02F1/1339 , G02F1/1333
Abstract: A reliability of seal portion of a liquid crystal display device can be improved by the following structure. A liquid crystal display device includes: a TFT substrate which includes a display region and a terminal part, and has an inorganic insulating film formed on an organic passivation film and an alignment film formed over the inorganic insulating film; a counter substrate, the TFT substrate and the counter substrate bonded together by a sealing material formed at a seal part surrounding the display region; and a liquid crystal sealed inside. At the seal part, a transparent conductive oxide film is formed between the inorganic insulating film and the alignment film. The transparent conductive oxide film exists inside an edge of the TFT substrate and hence, the edge of the TFT substrate is free of the transparent conductive oxide film.
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公开(公告)号:US20200225805A1
公开(公告)日:2020-07-16
申请号:US16828166
申请日:2020-03-24
Applicant: Japan Display Inc.
Inventor: Hayato Kurasawa , Shoji Hinata , Toshinori Uehara , Hiroshi Mizuhashi , Yuji Suzuki , Yasuhiro Kanaya
Abstract: Included are a first cover base including an alkali glass layer, a first alkali-free glass layer provided on one face of the alkali glass layer, and a second alkali-free glass layer provided on another face of the alkali glass layer and a sensor that is provided on the first alkali-free glass layer of the first cover base and includes a plurality of first electrodes configured to detect the unevenness of a surface of an object to be detected that comes into contact with or close to the first cover base and a switching element. At least the first electrodes are formed above the first alkali-free glass layer and in a transmissive area that passes an image.
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公开(公告)号:US10120253B2
公开(公告)日:2018-11-06
申请号:US15834388
申请日:2017-12-07
Applicant: Japan Display Inc.
Inventor: Motoharu Miyamoto , Teppei Yamada , Yasuhiro Kanaya
IPC: G02F1/1362 , H01L27/12 , G02F1/1368
Abstract: A display device is provided with a pixel and a dummy pixel including a gate line and a signal line. The dummy pixel includes the gate line and a dummy semiconductor layer crossing the gate line through an insulating layer. The dummy semiconductor layer is electrically separated from the dummy semiconductor layer of the dummy pixel adjacent in the Y direction dummy pixel. The dummy pixel further includes a dummy signal line extending in the Y direction. The dummy signal line is connected to the dummy semiconductor layer through a plurality of contact holes. The contact holes are arranged with the gate line interposed between them in plan view.
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