Abstract:
A method and apparatus for gray level dynamic switching. The method is applied to driving a display with at least one pixel. In the method of the present invention, a gray level sequence SG is provided. SG sequentially represents two or more desired gray levels Go(1), . . . , Go(T) of the pixel at consecutive time frames 1, . . . , T and comprises a current gray level Go(t) and a previous gray level Go(t−1) corresponding to time frames t and t−1, respectively. Then, the pixel is driven with an optimized driving force Vd(t) to change the pixel forward to a state corresponding to Go(t) according to Go(t) and Go(t−1). In the present invention, the optimized driving voltage Vd(t) is determined by equations of Vd(t)=Vo(t−1)+ODV and Vd(t)=a×Gd(m)3+b×Gd(m)2+c×Gd(m)+d, wherein the voltage ODV is a minimum voltage capable of obtaining one gray level transition in a determined response time.
Abstract:
A light source and a substrate are placed above and below a mask having a mask pattern thereon, respectively. Relative to the mask, the light source is moved in a first direction at a first speed, and the substrate is moved in a second direction at a second speed. The light of the light source transfers the mask pattern to a photoresist layer on the substrate, and forms a photoresist pattern thereof.
Abstract:
A liquid crystal display panel comprises a first substrate, a second substrate, a sealant, a liquid crystal layer, and a light-shielding layer, wherein the sealant is disposed between the first substrate and the second substrate; the liquid crystal layer is disposed among the first substrate, the second substrate and the sealant; and the light shielding layer is disposed on a surface of the first substrate but notin contact with the liquid crystal layer.
Abstract:
A liquid crystal display panel with reduced flicker comprises an active matrix substrate equipped with a plurality of thin film transistors. The active matrix substrate has an active area that is formed with a plurality of first signal lines and a plurality of second signal lines crossing each other. The active area includes a plurality of pixels arranged in a matrix. There are outer-lead bonding areas around the active area. There are a plurality of pad areas within the outer-lead bonding areas. A plurality of second wires arranged in a fan-out configuration extend from the pad areas and stretch toward the active area. The second wires are connected to their respective first signal lines by their serpentine or zigzag routes resulting in various wire lengths. A frame-like lead overlaps the second wires, and a capacitor exists between each of the second wires and the closed frame-like lead. The induced capacitor and the resistance of the corresponding second wire together result in a compensation effect so as to uniform the time constants of the plurality of first signal lines.
Abstract:
An in-plane switching liquid crystal display with an alignment free structure. In each pixel area, at least one floating metal layer is disposed between two common electrodes and patterned on the same plane with the common electrodes, and at least one pixel electrode is disposed between the two common electrodes and covers the floating metal layer. The center of the pixel electrode is aligned to the center of the floating metal layer, and each interval between two adjacent common electrode and pixel electrode is fixed at a constant.
Abstract:
A method for defining plural windows with different etching depths simultaneously is disclosed. The method includes steps of (a) forming a photoresist on a substrate having a multiple film structure thereon, (b) exposing a first region of the photoresist to a first exposure dose and a second region of the photoresist to a second exposure dose, (c) obtaining different remaining thickenesses of the photoresist on the first region and the second region by a development, and (d) etching the first region and the second region of the photoresist for forming the plural windows with different etching depths of the multiple film structure.
Abstract:
A simplified BCE process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique, the masking step for patterning an etch stopper layer can be omitted. By forming a pixel electrode layer before a data metal layer, a remaining portion of the data metal layer surrounding the pixel electrode can function as a black matrix after properly patterning and etching the data metal layer. The in-situ black matrix exempts from an additional step of providing a black matrix and solves the problem in alignment.
Abstract:
A liquid crystal display having a repair circuit structure and an array substrate of the liquid crystal display are provided. Each of the repair lines of the repair circuit comprises a front repair line portion arranged to cross with a front data line portion in a substantially perpendicular manner, an end repair line portion arranged to cross with an end data line portion in a substantially perpendicular manner, and an intermediate repair line portion connecting the front and end repair line portions. At least two repair lines in the end repair line portion are positioned in different layers so that a parasitic capacitance between respective repair lines in the repair circuit structure can be reduced and signal transmission quality can be ensured.
Abstract:
A liquid crystal display having a repair line structure and an array substrate of the liquid crystal display are provided. The repair line comprises a front repair line portion arranged to at least partially overlap a front portion of a first signal line, an end repair line portion arranged to at least partially overlap an end portion of the first signal line, and an intermediate repair line portion electrically connecting the front and end repair line portions. The front repair line portion comprises at least a first signal connection line and an external line which are electrically isolated when the repair line has not been used to repair a defect in the first signal line.
Abstract:
An array substrate comprises a scanning line; a data line crossing the scanning line; a pixel electrode; a common electrode; and a Thin Film Transistor comprising a gate electrode connected to the scanning line, a source electrode connected to the data line and a drain electrode connected to the pixel electrode, the drain electrode and the scanning line forming a first capacitor therebetween. The array substrate further comprises an auxiliary capacitor which is in parallel with the first capacitor.