摘要:
A graphics data-processing pipeline including a geometry processor and a fragment processor. The graphics data-processing pipeline being configured to render stencil data and to output the stencil data in a format compatible with input to the fragment processor. An output of the graphics data-processing pipeline is written to local memory and the output is subsequently read using the fragment processor without host processor intervening usage to format the stencil data or process the stencil data.
摘要:
A method is provided for processing multiple types of pixel component representations. The method first includes identifying a plurality of texels in a texture pattern grid that correspond to a pixel. Thereafter, information components of the pixel, i.e. R, G, B, and &agr; are multiplied if the information components of the pixel are in a postmultiplied representation. Further, a colorkeyed replacement operation is carried out if the information components of the pixel are in a colorkeyed representation and at least one of the texels substantially matches a colorkey. Next, a position is interpolated on the texture pattern grid between the texels that corresponds to the pixel. Finally, the information components of the pixel are filtered.
摘要:
A graphics pipeline including a rasterizing stage producing diffuse color values; a plurality of texture stages producing texture values defining a particular texture; a combiner stage for combining four of a plurality of selectable input values including diffuse color values, texture values furnished by a plurality of texture stages, and proportions for combination of the selectable input values; the combiner stage being capable of providing a result equivalent to a sum of products of any two sets of input values, and a product of two input values.
摘要:
The circuit generates an output value of an N-dimensional basis function. The circuit includes a string of sub-circuits, each sub-circuit computing a one-dimensional basis function. Each lower dimension sub-circuit is coupled to the adjacent higher dimension circuit, such that the current output is utilized as the input bias current to the adjacent higher dimension circuit. The coupling of sub-circuits in this manner provides the computation of the product of the 1-dimension basis functions produced by each of the sub-circuits.