Method and apparatus for processing stencil data using a programmable graphics processor
    41.
    发明授权
    Method and apparatus for processing stencil data using a programmable graphics processor 有权
    使用可编程图形处理器处理模板数据的方法和装置

    公开(公告)号:US07142215B1

    公开(公告)日:2006-11-28

    申请号:US10386751

    申请日:2003-03-11

    IPC分类号: G06T1/20 G06T1/00 G09G5/00

    CPC分类号: G06T1/20 G06T15/005

    摘要: A graphics data-processing pipeline including a geometry processor and a fragment processor. The graphics data-processing pipeline being configured to render stencil data and to output the stencil data in a format compatible with input to the fragment processor. An output of the graphics data-processing pipeline is written to local memory and the output is subsequently read using the fragment processor without host processor intervening usage to format the stencil data or process the stencil data.

    摘要翻译: 包括几何处理器和片段处理器的图形数据处理流水线。 图形数据处理流水线被配置为呈现模板数据并以与片段处理器的输入兼容的格式输出模板数据。 将图形数据处理流水线的输出写入本地存储器,随后使用片段处理器读取输出,而无需主机处理器中介使用以格式化模板数据或处理模板数据。

    Method and apparatus for processing multiple types of pixel component representations including processes of premultiplication, postmultiplication, and colorkeying/chromakeying
    42.
    发明授权
    Method and apparatus for processing multiple types of pixel component representations including processes of premultiplication, postmultiplication, and colorkeying/chromakeying 有权
    用于处理多种类型的像素分量表示的方法和装置,包括预乘法,后乘法和colorkeying / chromakeying的过程

    公开(公告)号:US06577320B1

    公开(公告)日:2003-06-10

    申请号:US09273995

    申请日:1999-03-22

    申请人: David B. Kirk

    发明人: David B. Kirk

    IPC分类号: G09G500

    CPC分类号: G09G5/026 G09G2340/10

    摘要: A method is provided for processing multiple types of pixel component representations. The method first includes identifying a plurality of texels in a texture pattern grid that correspond to a pixel. Thereafter, information components of the pixel, i.e. R, G, B, and &agr; are multiplied if the information components of the pixel are in a postmultiplied representation. Further, a colorkeyed replacement operation is carried out if the information components of the pixel are in a colorkeyed representation and at least one of the texels substantially matches a colorkey. Next, a position is interpolated on the texture pattern grid between the texels that corresponds to the pixel. Finally, the information components of the pixel are filtered.

    摘要翻译: 提供了一种用于处理多种类型的像素分量表示的方法。 该方法首先包括识别纹理图案网格中对应于像素的多个纹素。 此后,如果像素的信息分量处于后乘数表示中,则像素的信息分量即R,G,B和α相乘。 此外,如果像素的信息分量处于colorkeyed表示并且纹素中的至少一个基本上与colorkey匹配,则执行colorkeyed替换操作。 接下来,在对应于像素的纹素之间的纹理图案网格上插入位置。 最后,滤波像素的信息分量。

    Graphics pipeline including combiner stages
    43.
    发明授权
    Graphics pipeline including combiner stages 有权
    图形流水线包括组合器阶段

    公开(公告)号:US06333744B1

    公开(公告)日:2001-12-25

    申请号:US09273975

    申请日:1999-03-22

    IPC分类号: G06T120

    CPC分类号: G06T15/005

    摘要: A graphics pipeline including a rasterizing stage producing diffuse color values; a plurality of texture stages producing texture values defining a particular texture; a combiner stage for combining four of a plurality of selectable input values including diffuse color values, texture values furnished by a plurality of texture stages, and proportions for combination of the selectable input values; the combiner stage being capable of providing a result equivalent to a sum of products of any two sets of input values, and a product of two input values.

    摘要翻译: 包括产生漫射色值的光栅化阶段的图形管线; 多个纹理阶段产生定义特定纹理的纹理值; 组合器级,用于组合多个可选输入值中的四个,包括漫射色值,由多个纹理阶段提供的纹理值,以及用于组合可选择输入值的比例; 组合器级能够提供相当于任意两组输入值的乘积之和的结果,以及两个输入值的乘积。

    N-dimensional basis function circuit
    44.
    发明授权
    N-dimensional basis function circuit 失效
    N维基函数电路

    公开(公告)号:US5341051A

    公开(公告)日:1994-08-23

    申请号:US981763

    申请日:1992-11-25

    申请人: David B. Kirk

    发明人: David B. Kirk

    IPC分类号: H03F1/22 H03F3/345 H03F3/45

    CPC分类号: H03F1/223 H03F3/345

    摘要: The circuit generates an output value of an N-dimensional basis function. The circuit includes a string of sub-circuits, each sub-circuit computing a one-dimensional basis function. Each lower dimension sub-circuit is coupled to the adjacent higher dimension circuit, such that the current output is utilized as the input bias current to the adjacent higher dimension circuit. The coupling of sub-circuits in this manner provides the computation of the product of the 1-dimension basis functions produced by each of the sub-circuits.

    摘要翻译: 电路产生N维基函数的输出值。 该电路包括一串子电路,每个子电路计算一维基函数。 每个下维子电路耦合到相邻的较高维度电路,使得电流输出被用作到相邻较高维度电路的输入偏置电流。 以这种方式的子电路的耦合提供了由每个子电路产生的1维基函数的乘积的计算。