公开(公告)号：USD580903S1

公开(公告)日：2008-11-18

申请号：US29289573

申请日：2007-07-25

申请人： Jong Hoon Oh ,  Young Ju Yeo ,  Chang Hwan Hwang

设计人： Jong Hoon Oh ,  Young Ju Yeo ,  Chang Hwan Hwang

公开(公告)号：US6026055A

公开(公告)日：2000-02-15

申请号：US906544

申请日：1997-08-05

申请人： Jong Hoon Oh

发明人： Jong Hoon Oh

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1018

摘要： A burst page access unit for a semiconductor memory device which has a plurality of memory cell arrays for storing bit data therein. The burst page access unit comprises a row decoder for decoding a row address signal from an address input line in response to a row address strobe signal to select a desired one of the memory cell arrays, an internal address counter for incrementing a column address signal from the address input line by one in response to a column address strobe signal to generate an internal column address signal, and a column decoding circuit for decoding the internal column address signal from the internal address counter to select a desired one of memory cells in the memory cell array selected by the row decoder. According to the present invention, the burst page access unit can enhance the successive data access speed to increase the bandwidth of the semiconductor memory device.

摘要翻译： 一种用于半导体存储器件的突发页访问单元，其具有用于存储位数据的多个存储单元阵列。 突发页面访问单元包括行解码器，用于响应于行地址选通信号来解码来自地址输入行的行地址信号，以选择所需的存储单元阵列;内部地址计数器，用于将列地址信号从 响应于列地址选通信号的地址输入一行一行以产生内部列地址信号;以及列解码电路，用于对来自内部地址计数器的内部列地址信号进行解码，以选择存储器中的期望的一个存储单元 单元阵列由行解码器选择。 根据本发明，突发页面访问单元可以增强连续的数据访问速度以增加半导体存储器件的带宽。

公开(公告)号：US5925113A

公开(公告)日：1999-07-20

申请号：US645674

申请日：1996-05-14

申请人： Jong Hoon Oh

发明人： Jong Hoon Oh

IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10 ,  G11C11/408 ,  G11C11/41 ,  G11C11/413 ,  G06F13/12 ,  G06F13/14

CPC分类号： G11C7/1018

摘要： A burst mode end detection unit comprising a first decoding circuit for pre-decoding external burst length data, a plurality of counters being reset in response to a reset signal to generate different counts in response to a clock signal in such a manner that the counts are sequentially incremented by one, the reset signal being generated when a burst mode is designated, a second decoding circuit for decoding output signals from the counters, and a comparison circuit for comparing an output signal from the first decoding circuit with an output signal from the second decoding circuit and detecting an end time of the burst mode in accordance with the compared result. According to the present invention, the burst mode end detection unit can accurately detect the end time of the burst mode and notify a synchronous DRAM of the detected burst mode end time. Therefore, the synchronous DRAM can rapidly perform the subsequent operation.

摘要翻译： 突发模式结束检测单元，包括用于对外部突发长度数据进行预解码的第一解码电路，响应于复位信号复位多个计数器，以响应于时钟信号产生不同的计数，使得计数为 顺序递增1，当突发模式被指定时产生复位信号，用于解码来自计数器的输出信号的第二解码电路，以及用于将来自第一解码电路的输出信号与来自第二解码电路的输出信号进行比较的比较电路 解码电路，并根据比较结果检测突发模式的结束时间。 根据本发明，突发模式结束检测单元可以精确地检测突发模式的结束时间，并将检测到的突发模式结束时间通知给同步DRAM。 因此，同步DRAM可以快速执行后续操作。