公开(公告)号：US20220351777A1

公开(公告)日：2022-11-03

申请号：US17552225

申请日：2021-12-15

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C7/06

Abstract: According to one embodiment, a semiconductor memory device includes a first string unit including a first memory string including a first selection transistor and a first memory cell coupled to the first selection transistor, a second string unit including a second memory string including a second selection transistor and a second memory cell coupled to the second selection transistor, a first select gate line, a second select gate line, a first bit line, a second bit line, and a first word line. Both of the first select gate line and the second select gate line are selected in a first read operation. The first select gate line is selected and the second select gate line is not selected in a second read operation.

公开(公告)号：US20210296298A1

公开(公告)日：2021-09-23

申请号：US17005535

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Hiroshi MAEJIMA ,  Kenichiro YOSHII ,  Takashi MAEDA ,  Hideo WADA

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.