-
公开(公告)号：US20250087270A1
公开(公告)日：2025-03-13
申请号：US18953248
申请日：2024-11-20
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
-
公开(公告)号：US20240420764A1
公开(公告)日：2024-12-19
申请号：US18732967
申请日：2024-06-04
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
IPC: G11C16/08 , H01L23/00 , H01L25/065 , H01L25/18 , H10B80/00
Abstract: According to one embodiment, a memory device includes: a first chip including a first memory cell array; a second chip in contact with the first chip and including a second memory cell array; and a third chip in contact with the second chip and including a control circuit. The first memory cell array includes first and second transistors coupled in series. The second memory cell array includes third and fourth transistors coupled in series. The control circuit includes: fifth, sixth, and seventh transistors respectively having first ends coupled to gates of the first, third, and second and fourth transistors; a first decoder configured to switch a state of the fifth transistor; and a second decoder configured to switch a state of the sixth transistor independently of the state of the fifth transistor.
-
公开(公告)号：US20240257876A1
公开(公告)日：2024-08-01
申请号：US18631556
申请日：2024-04-10
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
CPC classification number: G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/16
Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the first memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.
-
公开(公告)号：US20240005995A1
公开(公告)日：2024-01-04
申请号：US18340977
申请日：2023-06-26
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
CPC classification number: G11C16/10 , G11C5/02 , G11C5/063 , G11C16/0483 , G11C16/08 , G11C16/3418 , G11C16/3422 , G11C16/04
Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
-
公开(公告)号：US20230360703A1
公开(公告)日：2023-11-09
申请号：US18354484
申请日：2023-07-18
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
IPC: G11C16/04 , G11C5/06 , G11C7/06 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , G11C16/26 , G11C16/08 , H01L23/522 , H01L23/528
CPC classification number: G11C16/0483 , G11C5/063 , G11C7/06 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , G11C16/26 , G11C16/08 , H01L23/5226 , H01L23/528
Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.
-
Patent Agency Ranking
公开(公告)号：US20230352105A1
公开(公告)日：2023-11-02
申请号：US18332472
申请日：2023-06-09
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
CPC classification number: G11C16/3427 , G11C16/08 , G11C16/32 , G11C16/3418 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459
Abstract: A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
-
公开(公告)号：US20210082879A1
公开(公告)日：2021-03-18
申请号：US16806079
申请日：2020-03-02
Applicant: Kioxia Corporation
Inventor： Tomoya SANUKI , Hiroshi MAEJIMA , Tetsuaki UTSUMI
IPC: H01L25/065 , H01L25/18 , H01L23/00
Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.
-
公开(公告)号：US20240177774A1
公开(公告)日：2024-05-30
申请号：US18431361
申请日：2024-02-02
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
CPC classification number: G11C16/10 , G06F3/0614 , G06F3/0631 , G06F3/0652 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0246 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3418 , G06F2212/1032 , G06F2212/152 , G06F2212/214 , G06F2212/7202 , G11C2213/71
Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
-
公开(公告)号：US20240096419A1
公开(公告)日：2024-03-21
申请号：US18524458
申请日：2023-11-30
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
CPC classification number: G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C16/32
Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
-
公开(公告)号：US20230409241A1
公开(公告)日：2023-12-21
申请号：US18242521
申请日：2023-09-06
Applicant: Kioxia Corporation
Inventor： Hiroshi MAEJIMA
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06N3/08 , G11C16/0483 , G11C16/08
Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a first circuit which controls the plurality of bit lines according to first data, a source line commonly connected to first ends of the plurality of bit lines, and a second circuit which is connected to the source line and which detects second data according to a current amount in the source line.
-
-
-
-
-
-
-
-
-
Search Results
42
records
(took 0.021 seconds)
