公开(公告)号：US20240315024A1

公开(公告)日：2024-09-19

申请号：US18595092

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Kazushi HARA ,  Yefei HAN ,  Keisuke NAKATSUKA ,  Koichi SAKATA

IPC: H10B43/27 ,  H01L25/00 ,  H01L25/065 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L25/50 ,  H10B43/35 ,  H01L25/0657

Abstract: In one embodiment, a semiconductor device includes a stacked film including electrode layers and first insulators alternately in a first direction, a top layer of the stacked film being a second insulator that is one of the first insulators. The device further includes a columnar portion including a third insulator, a charge storage layer, a fourth insulator and a first semiconductor layer that are sequentially provided in the stacked film. The device further includes a metal layer provided on the stacked film and the columnar portion, electrically connected to the first semiconductor layer, and including one or more layers. An upper end of the columnar portion is provided at a height between upper and lower faces of the second insulator. A lower end of a highest layer among the one or more layers is provided at a position lower than the upper face of the second insulator.

公开(公告)号：US20240086077A1

公开(公告)日：2024-03-14

申请号：US18181824

申请日：2023-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

公开(公告)号：US20230395546A1

公开(公告)日：2023-12-07

申请号：US18065212

申请日：2022-12-13

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  G11C16/16

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  G11C16/16 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, in a semiconductor memory device, the first chip has plural memory cells provided at plural intersection positions where the plural first conductive layers and the plural first semiconductor films intersect each other. The second chip has plural memory cells provided at plural intersection positions where the plural second conductive layers and the plural second semiconductor films intersect each other. A first connection configuration and a second connection configuration are insulated from each other. The first connection configuration reaches the third chip from a first conductive layer that a tip of the first semiconductor film reaches among the plural first conductive layers. The second connection configuration reaches the third chip from a second conductive layer that a tip of the second semiconductor film reaches among the plural second conductive layers.

公开(公告)号：US20230197160A1

公开(公告)日：2023-06-22

申请号：US17898868

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Koji KOHARA ,  Keisuke NAKATSUKA

IPC: G11C16/10

CPC classification number: G11C16/10

Abstract: A data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.

公开(公告)号：US20220406742A1

公开(公告)日：2022-12-22

申请号：US17683083

申请日：2022-02-28

Applicant: KIOXIA CORPORATION

Inventor： Keisuke NAKATSUKA

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device includes first and second memory cell arrays. The first array includes a first semiconductor portion, extending in a first direction, on which a first memory cell and a first select transistor are formed, a first word line connected to the first cell, a first select gate line connected to the first transistor, and a first bit line connected to the first semiconductor portion. The second array includes a second semiconductor portion, extending along the first direction, on which a second memory cell and a second select transistor are formed, a second word line connected to the second cell, a second select gate line connected to the second transistor, and a second bit line connected to the second semiconductor portion. The first and second word lines are electrically connected, but the first and second select gate lines are not electrically connected.

公开(公告)号：US20220367371A1

公开(公告)日：2022-11-17

申请号：US17874565

申请日：2022-07-27

Applicant: KIOXIA CORPORATION

Inventor： Nobuyuki MOMO ,  Keisuke NAKATSUKA

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/482 ,  H01L25/065 ,  H01L23/522 ,  H01L25/00 ,  H01L27/08 ,  H01L27/07

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

公开(公告)号：US20220223552A1

公开(公告)日：2022-07-14

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: H01L23/00 ,  H01L23/544 ,  G06F11/07

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US20230307361A1

公开(公告)日：2023-09-28

申请号：US17901644

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Yasunori IWASHITA ,  Shinya ARAI ,  Keisuke NAKATSUKA ,  Hiroaki ASHIDATE

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11578 ,  H01L27/11551

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/11578 ,  H01L27/11551

Abstract: A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.

公开(公告)号：US20230307011A1

公开(公告)日：2023-09-28

申请号：US17901590

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Keita HASEGAWA ,  Keisuke NAKATSUKA

IPC: G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: G11C5/06 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a first chip, a second chip, and a multiple of bonding pads. The first chip has a multiple of memory pillars that penetrate a multiple of wiring layers in a first direction. The second chip is bonded to the first chip. The multiple of bonding pads are provided at a bonding face between the first chip and the second chip. The multiple of bonding pads include a first bonding pad that electrically connects a first memory pillar among the multiple of memory pillars to one of a multiple of transistors, and a second bonding pad that neighbors the first bonding pad when seen from the first direction, and which electrically connects a second memory pillar among the multiple of memory pillars to one of the multiple of transistors. The second memory pillar does not neighbor the first memory pillar when seen from the first direction.

公开(公告)号：US20230005938A1

公开(公告)日：2023-01-05

申请号：US17941605

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA

IPC: H01L27/1157 ,  H01L27/11578 ,  G11C5/06

Abstract: A semiconductor memory device according to an embodiment includes first to ninth conductive layers, first and second insulating members, and first to fourth pillars. A distance between the first and second pillars in a cross section including the second conductive layer and the sixth conductive layer is smaller than a distance between the first and second pillars in a cross section including the third conductive layer and the seventh conductive layer. A distance between the third and fourth pillars in a cross section including the fourth conductive layer and the eighth conductive layer is greater than a distance between the third and fourth pillars in a cross section including the fifth conductive layer and the ninth conductive layer.