公开(公告)号：US06330249B1

公开(公告)日：2001-12-11

申请号：US09572512

申请日：2000-05-17

申请人： Katsumi Matsuno ,  Ichiro Kubota ,  Minobu Hayashi ,  Hisato Shima

发明人： Katsumi Matsuno ,  Ichiro Kubota ,  Minobu Hayashi ,  Hisato Shima

IPC分类号： H04J302

CPC分类号： H04L12/407 ,  H04L12/40013 ,  H04L12/40032 ,  H04L12/40052 ,  H04L12/40058 ,  H04L12/40065 ,  H04L12/40117 ,  H04L12/403 ,  H04L12/44 ,  H04L12/6418 ,  H04L41/00

摘要： A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

摘要翻译： 总线管理节点11具有使用信道REG1的寄存器和总线容量寄存器REG2。 在开始同步通信之前，每个节点12向使用中的信道REG1的寄存器和用于使用REG1的信道的寄存器发送读出命令，以便读出其内容以确定未使用的信道的数量，并且 剩余容量。 如果存在任何未使用的信道和任何剩余总线容量，则节点12向这些寄存器REG1和REG2发送写入命令，使得要被使用的信道的数目和要使用的总线的容量将被存储 在使用REG1和总线容量寄存器REG2的通道的寄存器中。 这使得能够在执行连接到总线的多个节点之间的同步通信的系统中容易地实现总线管理。

公开(公告)号：US06237120B1

公开(公告)日：2001-05-22

申请号：US08368758

申请日：1995-01-04

申请人： Keiichiro Shimada ,  Katsumi Matsuno ,  Sunao Furui

发明人： Keiichiro Shimada ,  Katsumi Matsuno ,  Sunao Furui

IPC分类号： G01R3128

CPC分类号： G06F9/268 ,  G06F8/66 ,  G06F9/328 ,  G06F11/08 ,  G06F11/1402

摘要： A micro-controller integrated on a single substrate and which includes a read-only information memory for storing firmware, an address controller for performing address control, and an input port for inputting information supplied thereto from a source external to the substrate further incorporates a correcting information storage memory for receiving correcting information input thereto from the source external to the substrate through the input port and storing the correcting information upon an initialization of the micro-controller, wherein the correcting information is indicative of a modification for a defective information part stored in the read-only information storage memory, and a switching circuit for selectively switching the access by the address controller from the defective information part in the read-only information storage memory to the correcting information in the correcting information storage memory.

摘要翻译： 一种集成在单个基板上的微控制器，其包括用于存储固件的只读信息存储器，用于执行地址控制的地址控制器和用于输入从源于外部的源提供给其的信息的输入端口进一步包括校正 信息存储存储器，用于通过所述输入端口从所述基板外部的源接收从其输入的校正信息，并且在所述微控制器的初始化时存储所述校正信息，其中所述校正信息指示存储在所述微控制器中的缺陷信息部分的修改 只读信息存储存储器和用于选择性地将地址控制器的访问从只读信息存储存储器中的缺陷信息部分切换到校正信息存储存储器中的校正信息的切换电路。

公开(公告)号：US5995489A

公开(公告)日：1999-11-30

申请号：US988118

申请日：1997-12-10

申请人： Katsumi Matsuno ,  Ichiro Kubota ,  Minobu Hayashi ,  Hisato Shima

发明人： Katsumi Matsuno ,  Ichiro Kubota ,  Minobu Hayashi ,  Hisato Shima

IPC分类号： H04L12/40 ,  H04L12/403 ,  H04L12/64 ,  H04J3/14

CPC分类号： H04L12/407 ,  H04L12/24 ,  H04L12/40013 ,  H04L12/40032 ,  H04L12/40058 ,  H04L12/40065 ,  H04L12/40117 ,  H04L12/403 ,  H04L12/6418 ,  H04L41/00 ,  H04L12/40052 ,  H04L12/44

摘要： A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

摘要翻译： 总线管理节点11具有使用信道REG1的寄存器和总线容量寄存器REG2。 在开始同步通信之前，每个节点12向使用中的信道REG1的寄存器和用于使用REG1的信道的寄存器发送读出命令，以便读出其内容以确定未使用的信道的数量，并且 剩余容量。 如果存在任何未使用的信道和任何剩余总线容量，则节点12向这些寄存器REG1和REG2发送写入命令，使得要被使用的信道的数量和要使用的总线的容量将被存储 在使用REG1和总线容量寄存器REG2的通道的寄存器中。 这使得能够在执行连接到总线的多个节点之间的同步通信的系统中容易地实现总线管理。

公开(公告)号：US5978360A

公开(公告)日：1999-11-02

申请号：US819021

申请日：1997-03-17

申请人： Katsumi Matsuno ,  Ichiro Kubota ,  Minobu Hayashi ,  Hisato Shima

发明人： Katsumi Matsuno ,  Ichiro Kubota ,  Minobu Hayashi ,  Hisato Shima

IPC分类号： H04L12/40 ,  H04L12/403 ,  H04L12/64 ,  H04J3/14

CPC分类号： H04L12/407 ,  H04L12/24 ,  H04L12/40013 ,  H04L12/40032 ,  H04L12/40058 ,  H04L12/40065 ,  H04L12/40117 ,  H04L12/403 ,  H04L12/6418 ,  H04L41/00 ,  H04L12/40052 ,  H04L12/44

摘要： A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

公开(公告)号：US5949761A

公开(公告)日：1999-09-07

申请号：US884752

申请日：1997-06-30

申请人： Katsumi Matsuno ,  Ichiro Kubota ,  Minobu Hayashi ,  Hisato Shima

发明人： Katsumi Matsuno ,  Ichiro Kubota ,  Minobu Hayashi ,  Hisato Shima

IPC分类号： H04L12/40 ,  H04L12/403 ,  H04L12/64 ,  H04J3/16

CPC分类号： H04L12/407 ,  H04L12/24 ,  H04L12/40013 ,  H04L12/40032 ,  H04L12/40058 ,  H04L12/40065 ,  H04L12/40117 ,  H04L12/403 ,  H04L12/6418 ,  H04L41/00 ,  H04L12/40052 ,  H04L12/44

摘要： A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

摘要翻译： 总线管理节点11具有使用信道REG1的寄存器和总线容量寄存器REG2。 在开始同步通信之前，每个节点12向使用REG1的信道的寄存器发送读出命令，并且向使用REG1的信道的寄存器发送读出命令，以便读出其内容以确定未使用的信道的数量，并且 剩余容量如果存在任何未使用的信道和任何剩余总线容量，则节点12向这些寄存器REG1和REG2发送写入命令，使得正在使用的信道的数量和正在使用的总线的容量将被 存储在使用REG1和总线容量寄存器REG2的通道的寄存器中。 这使得能够在执行连接到总线的多个节点之间的同步通信的系统中容易地实现总线管理。

公开(公告)号：US5742361A

公开(公告)日：1998-04-21

申请号：US753761

申请日：1996-11-29

申请人： Junko Nakase ,  Yukio Fujii ,  Hiroshi Gunji ,  Katsumi Matsuno

发明人： Junko Nakase ,  Yukio Fujii ,  Hiroshi Gunji ,  Katsumi Matsuno

IPC分类号： H04N21/236 ,  H04N21/2368 ,  H04N21/434 ,  H04N7/24

CPC分类号： H04N21/8547 ,  H04N21/434 ,  H04N21/4345 ,  H04N21/44016

摘要： A data demultiplexer includes a write controller, a memory, an analyzing processing unit, and transfer control units. The write controller writes packets which have arrived thereat into the memory in the order of arrival and sends the write information to the analyzing processing unit. The analyzing processing unit analyzes packets in the order of arrival on the basis of the write information and sends only the result of analysis to the transfer control units. On the basis of the result of analysis, the transfer control units send data read from the memory in the order of packet arrival to the decoder. A data demultiplexer capable of reducing the processing in the analyzing processing unit can be provided.

摘要翻译： 数据解复用器包括写入控制器，存储器，分析处理单元和传送控制单元。 写入控制器按照到达顺序将到达的数据包写入到存储器中，并将写入信息发送到分析处理单元。 分析处理单元基于写入信息按照到达顺序分析分组，并且仅将分析结果发送到传送控制单元。 基于分析结果，传送控制单元按照分组到达解码器的顺序从存储器读出数据。 可以提供能够减少分析处理单元中的处理的数据解复用器。

公开(公告)号：US5471481A

公开(公告)日：1995-11-28

申请号：US61731

申请日：1993-05-17

申请人： Koji Okumoto ,  Katsumi Matsuno ,  Toru Shiono ,  Toshitaka Senuma ,  Tokuya Fukuda ,  Shinji Takada

发明人： Koji Okumoto ,  Katsumi Matsuno ,  Toru Shiono ,  Toshitaka Senuma ,  Tokuya Fukuda ,  Shinji Takada

IPC分类号： G01R31/3185 ,  G06F11/25

CPC分类号： G01R31/318586 ,  G01R31/318555

摘要： A method of testing an electronic apparatus which eliminates a control signal line for setting an integrated circuit to a test mode and a test mode select terminal of an external terminal section and wherein fetching of test data and transfer of the thus fetched test data are performed in an integrated operation. In each of the integrated circuits, a boundary scan control circuit discriminates a category code at the top of data inputted from a serial input terminal to control a pair of switching circuits. When the category code represents a test mode, predetermined terminals of the switching circuits are selected so that input data are sent out to boundary scan cells. Fetching of parallel data from parallel input terminals and transfer to the boundary scan cells are performed at a time.

摘要翻译： 一种测试电子设备的方法，该电子设备消除了用于将集成电路设置为测试模式的控制信号线和外部终端部分的测试模式选择终端，并且其中获取测试数据并将如此获取的测试数据的传送执行在 综合运作。 在每个集成电路中，边界扫描控制电路鉴别从串行输入端输入的数据的顶部的类别码，以控制一对开关电路。 当类别代码表示测试模式时，选择开关电路的预定端子，使得输入数据被发送到边界扫描单元。 一次从并行输入端子取出并行数据并传送到边界扫描单元。