公开(公告)号：US20240345772A1

公开(公告)日：2024-10-17

申请号：US18616970

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Roberto Izzi ,  Nicola Colella ,  Luca Porzio ,  Marco Onorato

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

公开(公告)号：US12112065B2

公开(公告)日：2024-10-08

申请号：US17752354

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Roberto Izzi ,  Luca Porzio ,  Marco Onorato

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

公开(公告)号：US20240036977A1

公开(公告)日：2024-02-01

申请号：US17874952

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Ferdinando Pascale ,  Roberto Izzi ,  Marco Onorato ,  Erminio Di Martino

IPC: G06F11/14 ,  G06F1/24 ,  G06F9/4401

CPC classification number: G06F11/1417 ,  G06F1/24 ,  G06F9/4405

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

公开(公告)号：US20230367663A1

公开(公告)日：2023-11-16

申请号：US18137895

申请日：2023-04-21

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Alessandro Orlando ,  Danilo Caraccio ,  Roberto Izzi

IPC: G06F11/07 ,  G06F11/30

CPC classification number: G06F11/073 ,  G06F11/0772 ,  G06F11/076 ,  G06F11/0781 ,  G06F11/3037

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.

公开(公告)号：US11755490B2

公开(公告)日：2023-09-12

申请号：US17122174

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Luca Porzio ,  Roberto Izzi ,  Jonathan S. Parry

IPC: G06F12/0873 ,  G06F12/0891 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0873 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0891 ,  G06F2212/7201

Abstract: Methods, systems, and devices for unmap operation techniques are described. A memory system may include a volatile memory device and a non-volatile memory device. The memory system may receive a set of unmap commands that each include a logical block address associated with unused data. The memory system may determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system may select a first procedure for performing the set of unmap commands different from a second procedure (e.g., a default procedure) for performing the set of unmap commands and may perform the set of unmap commands using the first procedure. If the one or more parameters do not satisfy the threshold, the memory system may perform the set of unmap commands using the second procedure.

公开(公告)号：US20230259291A1

公开(公告)日：2023-08-17

申请号：US17651215

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Roberto Izzi ,  Christian M. Gyllenskog ,  Giuseppe Cariello ,  Jonathan S. Parry ,  Reshmi Basu

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0632 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/7201

Abstract: Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.

公开(公告)号：US20230195475A1

公开(公告)日：2023-06-22

申请号：US17645687

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Luca Porzio ,  Roberto Izzi ,  Francesco Falanga ,  Nadav Grosz ,  Massimo Iaculo

IPC: G06F9/4401 ,  G06F3/06

CPC classification number: G06F9/4406 ,  G06F3/0644 ,  G06F3/061 ,  G06F3/0683

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

公开(公告)号：US20230195374A1

公开(公告)日：2023-06-22

申请号：US17556066

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Roberto Izzi ,  Nicola Colella ,  Luca Porzio ,  Marco Onorato

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

公开(公告)号：US20220188237A1

公开(公告)日：2022-06-16

申请号：US17122174

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Luca Porzio ,  Roberto Izzi ,  Jonathan S. Parry

IPC: G06F12/0873 ,  G06F12/0891 ,  G06F12/02 ,  G06F12/06

Abstract: Methods, systems, and devices for unmap operation techniques are described. A memory system may include a volatile memory device and a non-volatile memory device. The memory system may receive a set of unmap commands that each include a logical block address associated with unused data. The memory system may determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system may select a first procedure for performing the set of unmap commands different from a second procedure (e.g., a default procedure) for performing the set of unmap commands and may perform the set of unmap commands using the first procedure. If the one or more parameters do not satisfy the threshold, the memory system may perform the set of unmap commands using the second procedure.

公开(公告)号：US20200293211A1

公开(公告)日：2020-09-17

申请号：US16890511

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06

Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.