公开(公告)号：US20220336028A1

公开(公告)日：2022-10-20

申请号：US17234502

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C16/24 ,  G11C7/06 ,  G11C7/10

Abstract: A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

公开(公告)号：US20220189570A1

公开(公告)日：2022-06-16

申请号：US17247435

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US20210391016A1

公开(公告)日：2021-12-16

申请号：US16946274

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/12 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08 ,  G11C16/34

Abstract: A processing device in a memory system initiates a program operation on the memory device, the program operation comprising a seeding phase. The processing device further causes a seeding voltage to be applied to a string of memory cells in a data block of the memory device during the seeding phase of the program operation and causes a positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase. Each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines comprising a selected word line associated with the program operation.