摘要:
Phase and amplitude offsets of a multicarrier transceiver may be reduced by measuring receiver amplitude and phase mismatches of receiver radio-frequency (RF) circuitry by performing a fast Fourier transform (FFT) on a receiver calibration signal.
摘要:
Embodiments of a multicarrier transmitter and method of generating an RF signal for transmission are generally described herein. Other embodiments may be described and claimed. In some embodiments, a multicarrier transmitter generates RF signals for transmission using non-linear switching power amplifiers to amplify outphased switching waveforms allowing the multicarrier transmitter to operate more efficiently than some conventional multicarrier transmitters.
摘要:
The invention concerns 2-oxo-1-pyrrolidine derivatives and a process for preparing them and their uses. The invention also concerns a process for preparing α-ethyl-2-oxo-1-pyrrolidine acetamide derivatives from unsaturated 2-oxo-1-pyrrolidine derivatives. Particularly the invention concerns novel intermediates and their use in methods for the preparation of S-α-ethyl-2oxo-1-pyrrolidine acetamide.
摘要:
Briefly, some embodiments of the invention provide devices, systems and methods of crosstalk cancellation. For example, an apparatus may include a first transmission path to carry a first signal with information to be transmitted; a second transmission path to carry a second signal with information to be transmitted; a scaler associated with said first transmission path to scale said first signal into a scaled first signal; and a combiner to combine said scaled first signal and said second signal into a combined second signal on said second transmission path.
摘要:
Briefly, exemplary embodiments of the invention may provide devices and methods to provide precise and/or low phase-noise quadrature oscillation signals. A quadrature oscillator in accordance with an exemplary embodiment of the invention may include, for example, a phase-shift generator to provide a phase-shift of substantially π/2 radians to an oscillation signal between a first oscillation tank, which provides substantially no phase-shift, and a second oscillation tank.
摘要:
A strained-silicon voltage controlled oscillator (VCO) includes a first p-channel metal oxide semiconductor (PMOS) device having a strained-silicon layer coupled to a second PMOS device having a strained-silicon layer.
摘要:
A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
摘要:
A semiconductor device or a circuit includes a controllable oscillator and circuitry that senses a voltage which may control the controllable oscillator and digitally controls a gain compensation, adaptively compensating for a drop in a gain against overall loop gain within a closed loop. In one embodiment, a single supply source may be used to power the closed loop while a variable gain stage that is digitally controllable may adjust the gain in a feed-forward manner based on the drop.
摘要:
A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
摘要:
A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.