公开(公告)号：US08498324B2

公开(公告)日：2013-07-30

申请号：US12604978

申请日：2009-10-23

申请人： Mark Hahm ,  Wei Luo ,  Arkady Molev-Shteiman

发明人： Mark Hahm ,  Wei Luo ,  Arkady Molev-Shteiman

IPC分类号： H04B1/707

CPC分类号： H04B1/7115 ,  H04B1/7107 ,  H04B2001/71077

摘要： Aspects of a method and system for interference suppression between multipath signals utilizing a programmable interface suppression module may include one or more processors and/or circuits that are operable to program an interference suppression module based on one or more interference cancellation parameters. A plurality of weighting factor values may be determined based on the one or more interference suppression parameters and a received plurality of multipath signals. A plurality of estimated signals may be generated based on the plurality of weighting factor values. A plurality of updated estimated signals may be generated based on the plurality of estimated signals. A plurality of interference suppressed signals may be generated based on the plurality of updated estimated signals and/or a plurality of updated residual signals.

摘要翻译： 利用可编程接口抑制模块的多径信号之间的干扰抑制的方法和系统的方面可以包括一个或多个处理器和/或电路，其可操作以基于一个或多个干扰消除参数对干扰抑制模块进行编程。 可以基于一个或多个干扰抑制参数和接收到的多个多径信号来确定多个加权因子值。 可以基于多个加权因子值来生成多个估计信号。 可以基于多个估计信号来生成多个更新的估计信号。 可以基于多个更新的估计信号和/或多个更新的残留信号来生成多个干扰抑制信号。

公开(公告)号：US08498321B2

公开(公告)日：2013-07-30

申请号：US12575840

申请日：2009-10-08

申请人： Mark Hahm

发明人： Mark Hahm

IPC分类号： H04B1/00

CPC分类号： H04B1/711 ,  H04B1/7107 ,  H04J11/004 ,  H04J11/0043 ,  H04J13/0044 ,  H04J13/0048

摘要： A wireless system may receive a plurality of multipath signals from a plurality of transmitters and sequentially process each of a plurality of data symbols in the received multipath signals utilizing a plurality of shared hardware modules within a chip. Desired information may be recovered from data transmitted by one or more of the transmitters utilizing the interference suppressed signal. Chips of data may be cell combined utilizing one or more of shared hardware modules. The shared modules may include channel rotation modules and sum and difference modules. One or more fast Hadamard transforms and/or inverse Hadamard transforms may be performed utilizing shared hardware modules. Data symbols may be interpolated, scrambled, descrambled, and/or weighted and added back utilizing the shared hardware modules.

摘要翻译： 无线系统可以从多个发射机接收多个多径信号，并利用芯片内的多个共享硬件模块来顺序处理接收到的多径信号中的多个数据符号中的每一个。 可以从利用干扰抑制信号的一个或多个发射机发送的数据中恢复所期望的信息。 数据芯片可以利用一个或多个共享硬件模块进行单元组合。 共享模块可以包括通道旋转模块和和差模块。 可以使用共享硬件模块来执行一个或多个快速Hadamard变换和/或逆Hadamard变换。 可以使用共享硬件模块对数据符号进行内插，加扰，解扰和/或加权并加回。

公开(公告)号：US20110096813A1

公开(公告)日：2011-04-28

申请号：US12604978

申请日：2009-10-23

申请人： Mark Hahm ,  Wei Luo ,  Arkady Molev-Shteiman

发明人： Mark Hahm ,  Wei Luo ,  Arkady Molev-Shteiman

IPC分类号： H04B1/707

CPC分类号： H04B1/7115 ,  H04B1/7107 ,  H04B2001/71077

摘要： Aspects of a method and system for interference suppression between multipath signals utilizing a programmable interface suppression module may include one or more processors and/or circuits that are operable to program an interference suppression module based on one or more interference cancellation parameters. A plurality of weighting factor values may be determined based on the one or more interference suppression parameters and a received plurality of multipath signals. A plurality of estimated signals may be generated based on the plurality of weighting factor values. A plurality of updated estimated signals may be generated based on the plurality of estimated signals. A plurality of interference suppressed signals may be generated based on the plurality of updated estimated signals and/or a plurality of updated residual signals.

摘要翻译： 利用可编程接口抑制模块的多径信号之间的干扰抑制的方法和系统的方面可以包括一个或多个处理器和/或电路，其可操作以基于一个或多个干扰消除参数对干扰抑制模块进行编程。 可以基于一个或多个干扰抑制参数和接收到的多个多径信号来确定多个加权因子值。 可以基于多个加权因子值来生成多个估计信号。 可以基于多个估计信号来生成多个更新的估计信号。 可以基于多个更新的估计信号和/或多个更新的残留信号来生成多个干扰抑制信号。

公开(公告)号：US20110065447A1

公开(公告)日：2011-03-17

申请号：US12573803

申请日：2009-10-05

申请人： Mark Hahm ,  Wei Luo

发明人： Mark Hahm ,  Wei Luo

IPC分类号： H04W72/00

CPC分类号： H04B1/7107 ,  H04B2201/70702 ,  H04W36/18

摘要： Aspects of a method and system for interference suppression using information from non-listened base stations are provided. In this regard, one or more circuits in a wireless communication device may be operable to receive a raw signal comprising one or more desired signals from one or more serving base transceiver stations (BTSs) and comprising one or more undesired signals from one or more non-listened BTSs. The one or more circuits may be operable to generate first estimate signals that estimate the one or more undesired signals as transmitted by the one or more non-listened BTSs, generate an interference suppressed version of the raw signal based on the first estimate signals, and recover the one or more desired signals from the interference suppressed version of the raw signal. The non-listened BTSs may comprise one or more BTSs that are not serving the wireless communication device and are not involved in a handoff of the wireless communication device.

摘要翻译： 提供了使用来自非收听基站的信息进行干扰抑制的方法和系统的方面。 在这方面，无线通信设备中的一个或多个电路可操作用于从一个或多个服务基站收发台（BTS）接收包括一个或多个所需信号的原始信号，并且包括一个或多个不需要的信号， 听众的BTS。 一个或多个电路可以用于产生估计由一个或多个非收听的BTS发送的一个或多个不需要的信号的第一估计信号，基于第一估计信号产生原始信号的干扰抑制版本;以及 从原始信号的干扰抑制版本恢复一个或多个期望的信号。 非收听的BTS可以包括一个或多个BTS，其不服务于无线通信设备，并且不参与无线通信设备的切换。

公开(公告)号：US20110065441A1

公开(公告)日：2011-03-17

申请号：US12575840

申请日：2009-10-08

申请人： Mark Hahm

发明人： Mark Hahm

IPC分类号： H04W72/08 ,  H04M1/00

CPC分类号： H04B1/711 ,  H04B1/7107 ,  H04J11/004 ,  H04J11/0043 ,  H04J13/0044 ,  H04J13/0048

摘要： A wireless system may receive a plurality of multipath signals from a plurality of transmitters and sequentially process each of a plurality of data symbols in the received multipath signals utilizing a plurality of shared hardware modules within a chip. Desired information may be recovered from data transmitted by one or more of the transmitters utilizing the interference suppressed signal. Chips of data may be cell combined utilizing one or more of shared hardware modules. The shared modules may include channel rotation modules and sum and difference modules. One or more fast Hadamard transforms and/or inverse Hadamard transforms may be performed utilizing shared hardware modules. Data symbols may be interpolated, scrambled, descrambled, and/or weighted and added back utilizing the shared hardware modules.

摘要翻译： 无线系统可以从多个发射机接收多个多径信号，并利用芯片内的多个共享硬件模块来顺序处理接收到的多径信号中的多个数据符号中的每一个。 可以从利用干扰抑制信号的一个或多个发射机发送的数据中恢复所期望的信息。 数据芯片可以利用一个或多个共享硬件模块进行单元组合。 共享模块可以包括通道旋转模块和和差模块。 可以使用共享硬件模块来执行一个或多个快速Hadamard变换和/或逆Hadamard变换。 可以使用共享硬件模块对数据符号进行内插，加扰，解扰和/或加权并加回。

公开(公告)号：US20110064122A1

公开(公告)日：2011-03-17

申请号：US12612272

申请日：2009-11-04

申请人： Mark Hahm ,  Wei Luo ,  Jun Wu

发明人： Mark Hahm ,  Wei Luo ,  Jun Wu

IPC分类号： H04B1/707 ,  H04B1/10

CPC分类号： H04B1/7107 ,  H04B2201/70702

摘要： Aspects of a method and system for processing signals utilizing a programmable interference suppression module are provided. In this regard, a received signal may be iteratively processed to generate an interference suppressed representation of the received signal. The iterative processing may comprise a weighting iteration; an addback weighting and un-addback iteration, and an addback iteration. The weighting iteration may comprise generating one or more first estimate signals that estimate user signals present in the received signal. The addback, weighting, and un-addback iteration may comprise generating one or more incremental estimate signals based on the one or more first estimate signals and the one or more second estimate signals. The addback iteration may comprise generating an interference suppressed representation of the received signal based on at least the one or more second estimate signals.

摘要翻译： 提供了利用可编程干扰抑制模块处理信号的方法和系统的方面。 在这点上，可以迭代地处理接收的信号以产生接收信号的干扰抑制表示。 迭代处理可以包括加权迭代; 附加加权和非加法迭代，以及附加回合。 加权迭代可以包括生成估计接收信号中存在的用户信号的一个或多个第一估计信号。 加法，加权和非附加迭代可以包括基于一个或多个第一估计信号和一个或多个第二估计信号来生成一个或多个增量估计信号。 附加迭代可以包括基于至少一个或多个第二估计信号来生成接收信号的干扰抑制表示。

公开(公告)号：US20060274715A1

公开(公告)日：2006-12-07

申请号：US11142213

申请日：2005-06-01

申请人： Mark Hahm ,  Li Chang ,  Michiel Lotter

发明人： Mark Hahm ,  Li Chang ,  Michiel Lotter

IPC分类号： H04J3/24

CPC分类号： H04L1/0051 ,  H04L1/0054 ,  H04L1/0066 ,  H04L1/1819 ,  H04L1/1845

摘要： A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives at least one set of IR samples from the memory, forms a turbo code word from the at least one set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric, performs de-rate matching, performs error detection operations, and extracts information from a MAC packet that it produces.

公开(公告)号：US20050094730A1

公开(公告)日：2005-05-05

申请号：US10869789

申请日：2004-06-16

申请人： Li Chang ,  Mark Hahm ,  Weiping Pan ,  Ruei-Shiang Suen

发明人： Li Chang ,  Mark Hahm ,  Weiping Pan ,  Ruei-Shiang Suen

IPC分类号： G09G5/00 ,  H04B1/66 ,  H04B7/185 ,  H04L12/56 ,  H04N7/12 ,  H04N7/18 ,  H04N7/26 ,  H04N7/36 ,  H04N7/50 ,  H04N11/02 ,  H04N11/04

CPC分类号： H04N21/6131 ,  H04N19/42 ,  H04N19/43 ,  H04N19/44 ,  H04N19/523 ,  H04N19/61 ,  H04N19/70 ,  H04N21/43637 ,  H04N2007/145 ,  H04W88/02

摘要： A video processor within a wireless terminal, that includes a video interface that receives incoming video information and that provides outgoing video information, a processing module operably coupled to the video interface, and a video accelerator module and a motion processing co-processor operably coupled to the processing module. The processing of the incoming video information and the outgoing video information is performed by the combination of the processing module, co-processor and the video accelerator module. Compute intensive operations may be offloaded from the processing module onto the video accelerator to improve overall system efficiency.

摘要翻译： 无线终端内的视频处理器，其包括接收输入视频信息并提供输出视频信息的视频接口，可操作地耦合到视频接口的处理模块，以及可操作地耦合到 处理模块。 通过处理模块，协处理器和视频加速器模块的组合来执行输入视频信息和输出视频信息的处理。 计算密集型操作可以从处理模块卸载到视频加速器上，以提高整体系统效率。