公开(公告)号：US09727336B2

公开(公告)日：2017-08-08

申请号：US13234785

申请日：2011-09-16

申请人： Michael K. Gschwind ,  Brett Olsson ,  Valentina Salapura

发明人： Michael K. Gschwind ,  Brett Olsson ,  Valentina Salapura

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F9/3013 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3016 ,  G06F9/30189

摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

公开(公告)号：US09411585B2

公开(公告)日：2016-08-09

申请号：US13234520

申请日：2011-09-16

申请人： Michael K. Gschwind ,  Brett Olsson

发明人： Michael K. Gschwind ,  Brett Olsson

IPC分类号： G06F9/30 ,  G06F9/302

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30185

摘要： A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be translated from one format to another format. If so determined, a convert machine instruction is executed that obtains a single precision datum in a first representation in a first format from a first register; converts the single precision datum of the first representation in the first format to a converted single precision datum of a second representation in a second format; and places the converted single precision datum in a second register.

公开(公告)号：US08458442B2

公开(公告)日：2013-06-04

申请号：US12548129

申请日：2009-08-26

申请人： Alexandre E. Eichenberger ,  Michael Karl Gschwind ,  John A. Gunnels ,  Fred Gehrung Gustavson ,  Brett Olsson

发明人： Alexandre E. Eichenberger ,  Michael Karl Gschwind ,  John A. Gunnels ,  Fred Gehrung Gustavson ,  Brett Olsson

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F9/3881 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3877 ,  G06F17/16

摘要： A structure (and method) including a plurality of coprocessing units and a controller that selectively loads data for processing on the plurality of coprocessing units, using a compound loading instruction. The compound loading instruction includes a plurality of low-level software instructions that preliminarily processes input data in a manner predetermined to simulate an effect of a single hardware loading instruction that would provide optimal loading of complex matrix data by loading input data in accordance with the effect of multiplying i·i=−1.

摘要翻译： 一种包括多个协处理单元和使用复合加载指令选择性地加载用于处理多个协处理单元的数据的控制器的结构（和方法）。 复合加载指令包括多个低级软件指令，其以预定的方式预先处理输入数据，以模拟单个硬件加载指令的效果，该硬件加载指令将通过根据效果加载输入数据来提供复合矩阵数据的最佳加载 乘以i·i = -1。

公开(公告)号：US20130073836A1

公开(公告)日：2013-03-21

申请号：US13234785

申请日：2011-09-16

申请人： Michael K. Gschwind ,  Brett Olsson ,  Valentina Salapura

发明人： Michael K. Gschwind ,  Brett Olsson ,  Valentina Salapura

IPC分类号： G06F9/30 ,  G06F9/302

CPC分类号： G06F9/3013 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3016 ,  G06F9/30189

摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

公开(公告)号：US20090198966A1

公开(公告)日：2009-08-06

申请号：US12023720

申请日：2008-01-31

申请人： Michael K. Gschwind ,  Brett Olsson

发明人： Michael K. Gschwind ,  Brett Olsson

IPC分类号： G06F9/30

CPC分类号： G06F9/3013 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145

摘要： A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file.

摘要翻译： 可以使用标量和SIMD指令来寻址单个寄存器文件。 也就是说，根据说明性实施例的多可寻址寄存器堆中的寄存器子集可以用不同的指令形式（例如标量指令，SIMD指令等）寻址，而整个寄存器组可以用另一形式 的指令，这里称为矢量 - 标量延伸（VSX）指令。 可以使用VSX指令形式在整个寄存器组上执行的操作集基本上类似于寄存器子集的操作集。 这种布置允许传统指令访问多址寻址寄存器文件内的寄存器子集，而新的指令即VSX指令可以访问多址寻址寄存器堆中的整个寄存器范围。

公开(公告)号：US20080086596A1

公开(公告)日：2008-04-10

申请号：US11538445

申请日：2006-10-04

申请人： Gordon T. Davis ,  Richard W. Doing ,  John D. Jabusch ,  M. V. V. Anil Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

发明人： Gordon T. Davis ,  Richard W. Doing ,  John D. Jabusch ,  M. V. V. Anil Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/6082

摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

摘要翻译： 单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。 描述了一种用于索引到高速缓存并选择所需行的机制。 对缓存中包含哪些行进行控制。 当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

公开(公告)号：US20080086595A1

公开(公告)日：2008-04-10

申请号：US11538458

申请日：2006-10-04

申请人： Gordon T. Davis ,  Richard W. Doing ,  John D. Jabusch ,  M. V. V. Anil Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

发明人： Gordon T. Davis ,  Richard W. Doing ,  John D. Jabusch ,  M. V. V. Anil Krishna ,  Brett Olsson ,  Eric F. Robinson ,  Sumedh W. Sathaye ,  Jeffrey R. Summers

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/3808 ,  G06F2212/1028 ,  Y02D10/13

摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.

摘要翻译： 单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。 通过引导访问存储在缓存中的行并相对于中央处理器时钟速度降低缓存时钟速度来节省功率。

公开(公告)号：US06202141B1

公开(公告)日：2001-03-13

申请号：US09098063

申请日：1998-06-16

申请人： Keith Everett Diefendorff ,  Pradeep Kumar Dubey ,  Ronald Ray Hochsprung ,  Brett Olsson ,  Hunter Ledbetter Scales, III

发明人： Keith Everett Diefendorff ,  Pradeep Kumar Dubey ,  Ronald Ray Hochsprung ,  Brett Olsson ,  Hunter Ledbetter Scales, III

IPC分类号： G06F9302

CPC分类号： G06F9/30014 ,  G06F9/30025 ,  G06F9/30036

摘要： A vector multiplication mechanism is provided that partitions vector multiplication operation into even and odd paths. In an odd path, odd data elements of first and second source vectors are selected, and multiplication operation is performed between each of the selected odd data elements of the first source vector and corresponding one of the selected odd data elements of the second source vector. In an even path, even data elements of the source vectors are selected, and multiplication operation is performed between each of the selected even data elements of the first source vector and corresponding one of the selected even data elements of the second source vector. Elements of resultant data of the two paths are merged together in a merge operation. The vector multiplication mechanism of the present invention preferably uses a single general-purpose register to store the resultant data of the odd path and the even path. In addition, computational overhead of the merge operation is amortized over a series of vector operations.

摘要翻译： 提供了向量乘法机制，其将矢量乘法运算分为偶数和奇数路径。 在奇数路径中，选择第一和第二源向量的奇数数据元素，并且在第一源向量的所选择的奇数数据元素和第二源向量的所选奇数数据元素中的相应一个之间执行乘法运算。 在偶数路径中，选择源向量的偶数数据元素，并且在第一源向量的所选择的偶数数据元素和第二源向量的所选择的偶数数据元素中的对应一个之间执行乘法运算。 两个路径的结果数据的元素在合并操作中合并在一起。 本发明的向量乘法机构优选地使用单个通用寄存器来存储奇数路径和偶数路径的结果数据。 此外，合并操作的计算开销在一系列向量操作中进行分摊。

公开(公告)号：US5890222A

公开(公告)日：1999-03-30

申请号：US368176

申请日：1995-01-04

申请人： Ramesh Chandra Agarwal ,  John Joseph Haddow Forrest ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson

发明人： Ramesh Chandra Agarwal ,  John Joseph Haddow Forrest ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F12/00

CPC分类号： G06F9/34 ,  G06F9/30098 ,  G06F9/35

摘要： In a data processing unit, an instruction is loaded. Such an instruction includes an operation code field for storing an operation code and at least one operand field, where the operand field includes an indirect addressing mode indicator for indicating enablement of an indirect addressing mode. If an indirect addressing mode is enabled, a general purpose register address is selected from an address field in an indirect register. Finally, the data processing unit addresses a selected one of the plurality of general purpose registers utilizing the general purpose register address during the execution of the operation code by the data processing unit.

摘要翻译： 在数据处理单元中，加载指令。 这样的指令包括用于存储操作码和至少一个操作数字段的操作码字段，其中操作数字段包括用于指示启用间接寻址模式的间接寻址模式指示符。 如果启用间接寻址模式，则从间接寄存器的地址字段中选择通用寄存器地址。 最后，在数据处理单元执行操作码期间，数据处理单元利用通用寄存器地址来寻址多个通用寄存器中的选定一个。

公开(公告)号：US5887183A

公开(公告)日：1999-03-23

申请号：US368173

申请日：1995-01-04

申请人： Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred G. Gustavson ,  Mark A. Johnson ,  Terry L. Lyon ,  Brett Olsson ,  James B. Shearer

发明人： Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred G. Gustavson ,  Mark A. Johnson ,  Terry L. Lyon ,  Brett Olsson ,  James B. Shearer

IPC分类号： G06F9/312 ,  G06F15/80

CPC分类号： G06F9/30043 ,  G06F15/8092 ,  G06F9/30036

摘要： A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

摘要翻译： 具有多个元素的向量存储在输入存储区域中，其中矢量元素以第一模式存储。 此后，元件以第一顺序从输入存储区域传送到向量寄存器接口单元。 从矢量寄存器接口单元，将元件传送到输出存储区域，并以多个预选图案之一存储在可寻址位置。 输入存储区域可以由高速缓冲存储器或寄存器阵列来实现。 输出存储区域可以用高速缓冲存储器或寄存器阵列来实现。 输入存储区域中的第一图案可以包括交替的实数和虚部元素。 多个预选图案可以包括相反的顺序图案，或者将实数元素和虚构元素分离成两个向量寄存器。